summaryrefslogtreecommitdiff
path: root/src/mainboard/compulab
diff options
context:
space:
mode:
authorNico Huber <nico.h@gmx.de>2020-03-22 20:12:13 +0100
committerNico Huber <nico.h@gmx.de>2020-03-24 20:36:36 +0000
commitd07ac8ee13ce7f1af5a9d9a5d2e194ab27b8fb9a (patch)
tree018e611167eebe530fe3e56656d8e9adea25c911 /src/mainboard/compulab
parente47132be6601bfd485076d6520e56a8b8ecb0737 (diff)
downloadcoreboot-d07ac8ee13ce7f1af5a9d9a5d2e194ab27b8fb9a.tar.xz
drivers/intel/gma: Ditch `link_frequency_270_mhz` setting
The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/compulab')
-rw-r--r--src/mainboard/compulab/intense_pc/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb
index 4717eca3eb..b333245da6 100644
--- a/src/mainboard/compulab/intense_pc/devicetree.cb
+++ b/src/mainboard/compulab/intense_pc/devicetree.cb
@@ -12,7 +12,6 @@
chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
- register "gfx.link_frequency_270_mhz" = "1"
register "gfx.ndid" = "3"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"