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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-26 02:02:00 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-01-09 01:06:00 +0100 |
| commit | 391622ae30d36ff6a666892d2da7eba67120a400 (patch) | |
| tree | 625c1276157b3d548817274751717b96fcd671b3 /src/mainboard/cubietech | |
| parent | 30c20e92a28c8a993baf41415c8a36410ca97c2d (diff) | |
| download | coreboot-391622ae30d36ff6a666892d2da7eba67120a400.tar.xz | |
cubieboard: Keep AHB clock within specs
The CPU was clocked at 384MHz in the bootblock, but the AHB bus has a
maximum rated frequency of 250MHz. Its clock needs to be divided to
keep it within spec. Overclocking the AHB bus hung the CPU when
memory was accessed.
Change-Id: I7cb9cdd1f126b3d5b0446fc68af79b54946bc2d3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4629
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/cubietech')
| -rw-r--r-- | src/mainboard/cubietech/cubieboard/bootblock.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 90dfd0d458..8899160d45 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -15,7 +15,7 @@ #define CPU_AHB_APB0_DEFAULT \ CPU_CLK_SRC_OSC24M \ | APB0_DIV_1 \ - | AHB_DIV_1 \ + | AHB_DIV_2 \ | AXI_DIV_1 #define GPH_STATUS_LEDS (1 << 20) | (1 << 21) @@ -33,7 +33,9 @@ static void cubieboard_set_sys_clock(void) /* Switch CPU clock to main oscillator */ write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg); - /* Configure the PLL1. The value is the same one used by u-boot */ + /* Configure the PLL1. The value is the same one used by u-boot + * P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz + */ write32(0xa1005000, &ccm->pll1_cfg); /* FIXME: Delay to wait for PLL to lock */ |