arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 7 insertions, 7 deletions

diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c
index 79d00189e8..e4a0313bd4 100644
--- a/src/mainboard/cubietech/cubieboard/bootblock.c
+++ b/src/mainboard/cubietech/cubieboard/bootblock.c
@@ -38,12 +38,12 @@ static void cubieboard_set_sys_clock(void)
 	struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
 
 	/* Switch CPU clock to main oscillator */
-	writel(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg);
+	write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT);
 
 	/* Configure the PLL1. The value is the same one used by u-boot
 	 * P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
 	 */
-	writel(0xa1005000, &ccm->pll1_cfg);
+	write32(&ccm->pll1_cfg, 0xa1005000);
 
 	/* FIXME: Delay to wait for PLL to lock */
 	u32 wait = 1000;
@@ -53,7 +53,7 @@ static void cubieboard_set_sys_clock(void)
 	reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
 	reg32 &= ~CPU_CLK_SRC_MASK;
 	reg32 |= CPU_CLK_SRC_PLL1;
-	writel(reg32, &ccm->cpu_ahb_apb0_cfg);
+	write32(&ccm->cpu_ahb_apb0_cfg, reg32);
 }
 
 static void cubieboard_setup_clocks(void)
@@ -62,12 +62,12 @@ static void cubieboard_setup_clocks(void)
 
 	cubieboard_set_sys_clock();
 	/* Configure the clock source for APB1. This drives our UART */
-	writel(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
-	       &ccm->apb1_clk_div_cfg);
+	write32(&ccm->apb1_clk_div_cfg,
+		APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0));
 
 	/* Configure the clock for SD0 */
-	writel(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1),
-	       &ccm->sd0_clk_cfg);
+	write32(&ccm->sd0_clk_cfg,
+		SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1));
 
 	/* Enable clock to SD0 */
 	a1x_periph_clock_enable(A1X_CLKEN_MMC0);