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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-08-12 15:00:51 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2009-08-12 15:00:51 +0000 |
| commit | 0588d19abef62dad63a7794a37bdd6a71c526d9e (patch) | |
| tree | 1c507caa1ffed6ceb73d3e13fc9b766a713d16e2 /src/mainboard/dell/s1850/devicetree.cb | |
| parent | 38cd29ebd7282333650cf11ed50c7f2fd4031e80 (diff) | |
| download | coreboot-0588d19abef62dad63a7794a37bdd6a71c526d9e.tar.xz | |
Kconfig!
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/dell/s1850/devicetree.cb')
| -rw-r--r-- | src/mainboard/dell/s1850/devicetree.cb | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb new file mode 100644 index 0000000000..4e93a3aefb --- /dev/null +++ b/src/mainboard/dell/s1850/devicetree.cb @@ -0,0 +1,71 @@ +chip northbridge/intel/e7520 # mch + device pci_domain 0 on + chip southbridge/intel/i82801er # i82801er + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + + # -> Bridge + device pci 1e.0 on end + + # -> ISA + device pci 1f.0 on + chip superio/nsc/pc8374 + device pnp 2e.0 off end + device pnp 2e.1 off end + device pnp 2e.2 off end + device pnp 2e.3 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.8 off end + end + end + # -> IDE + device pci 1f.1 on end + # -> SATA + device pci 1f.2 on end + device pci 1f.3 on end + + register "pirq_a_d" = "0x8a07030b" + register "pirq_e_h" = "0x85808080" + end + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + # Bus bridges and ioapics usually bus 1 + device pci 0.0 on + # On board gig e1000 + chip drivers/generic/generic + device pci 03.0 on end + device pci 03.1 on end + end + end + device pci 0.1 on end + device pci 0.2 on end + device pci 0.3 on end + end + end + device pci 04.0 on end + device pci 06.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604 # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604 # cpu 1 + device apic 6 on end + end + end + register "intrline" = "0x00070100" +end + |