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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-08-11 17:35:02 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-08-11 17:35:02 +0000 |
| commit | b339e10f04869a3d8da31e7d52831c32c57302a2 (patch) | |
| tree | 9876043ec4255e1dcf619890eba579872273564f /src/mainboard/dell/s1850 | |
| parent | 401c8d1da2a5292649498ec3a2c8414bd8ecd62c (diff) | |
| download | coreboot-b339e10f04869a3d8da31e7d52831c32c57302a2.tar.xz | |
Enable CBFS everywhere. All boards compiled for me (abuild tested),
and we will fix issues as they appear.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/dell/s1850')
| -rw-r--r-- | src/mainboard/dell/s1850/Config.lb | 2 | ||||
| -rw-r--r-- | src/mainboard/dell/s1850/Options.lb | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb index 90f0181888..645e8b916d 100644 --- a/src/mainboard/dell/s1850/Config.lb +++ b/src/mainboard/dell/s1850/Config.lb @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb index 199394a28b..72ad796059 100644 --- a/src/mainboard/dell/s1850/Options.lb +++ b/src/mainboard/dell/s1850/Options.lb @@ -130,7 +130,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 ## ## Use a small 8K stack @@ -147,7 +147,7 @@ default CONFIG_HEAP_SIZE=0x8000 ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ default CONFIG_CONSOLE_BTEXT=0 # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end |