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author | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-07-06 21:05:04 +0000 |
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committer | Myles Watson <mylesgw@gmail.com> | 2010-07-06 21:05:04 +0000 |
commit | eb50c7d922e91f0247b3705eccb2d2eec638c277 (patch) | |
tree | 2def570d089b2f6deb2beac165e18756a578e308 /src/mainboard/digitallogic/adl855pc | |
parent | 8376831eafc1be1175529fd21e0d2fe40339d4eb (diff) | |
download | coreboot-eb50c7d922e91f0247b3705eccb2d2eec638c277.tar.xz |
Re-integrate "USE_OPTION_TABLE" code.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/digitallogic/adl855pc')
-rw-r--r-- | src/mainboard/digitallogic/adl855pc/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/digitallogic/adl855pc/romstage.c | 3 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index 78da8f1b1b..31b27ed17a 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -5,6 +5,7 @@ config BOARD_DIGITALLOGIC_ADL855PC select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 424b2e1ed9..097ecde8f1 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -4,10 +4,9 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -//#include "option_table.h" #include <stdlib.h> #include "pc80/udelay_io.c" -#include "pc80/mc146818rtc_early.c" +#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" |