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authorStefan Reinauer <stepan@openbios.org>2006-03-17 22:48:23 +0000
committerStefan Reinauer <stepan@openbios.org>2006-03-17 22:48:23 +0000
commitdba3f846f0978812d081245d9e636cd434978067 (patch)
tree94f6ac9e3cef71e71aedb39e4b91c1227f83e79f /src/mainboard/digitallogic/msm586seg
parentf4001cd8a7d1e578e22a391150c4c446e13157c0 (diff)
downloadcoreboot-dba3f846f0978812d081245d9e636cd434978067.tar.xz
- sc520 updates. move PAR setup to mainboard auto.c
- some ts5300 code. Let's push this upstream for now. - fix a typo in device.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/digitallogic/msm586seg')
-rw-r--r--src/mainboard/digitallogic/msm586seg/auto.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/digitallogic/msm586seg/auto.c b/src/mainboard/digitallogic/msm586seg/auto.c
index 33c1cb9c41..1917fd097e 100644
--- a/src/mainboard/digitallogic/msm586seg/auto.c
+++ b/src/mainboard/digitallogic/msm586seg/auto.c
@@ -12,6 +12,34 @@
#include "ram/ramtest.c"
#include "cpu/x86/bist.h"
//#include "lib/delay.c"
+
+void setup_pars(void)
+{
+ volatile unsigned long *par;
+ /* as per the book: */
+ /* PAR register setup */
+ /* set up the PAR registers as they are on the MSM586SEG */
+ par = (unsigned long *) 0xfffef088;
+
+ /* NOTE: move this to mainboard.c ASAP */
+ *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
+ *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
+ *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
+ *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
+ *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
+ *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
+ *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
+ *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
+ *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
+ *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
+ *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
+ *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
+ *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
+ *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
+ *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
+ *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
+}
+
#include "cpu/amd/sc520/raminit.c"
typedef void (*lj)(void);
@@ -161,6 +189,8 @@ static inline void irqinit(void){
#endif
}
+
+
static void main(unsigned long bist)
{
volatile int i;