add the msm800srv ; put the usb in the right place.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 60 insertions, 0 deletions

diff --git a/src/mainboard/digitallogic/msm800sev/irq_tables.c b/src/mainboard/digitallogic/msm800sev/irq_tables.c
new file mode 100644
index 0000000000..4322e20e9b
--- /dev/null
+++ b/src/mainboard/digitallogic/msm800sev/irq_tables.c
@@ -0,0 +1,60 @@
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+#define ID_SLOT_PCI_NET		1			// ThinCan ethernet
+#define ID_SLOT_PCI_RSVD1	2           // reserved entry 1
+#define ID_SLOT_PCI_RSVD3	3           // reserved entry 2
+#define ID_SLOT_PCI_RSVD2	4			// reserved entry 3
+#define ID_EMBED_PCI		0xff		// onboard PCI device
+
+// CS5535 PCI INT[A-D] Interrupt Routing lines.
+#define NO_CONNECT			0			// not used
+#define CS_PCI_INTA			1			// PCI INTA
+#define CS_PCI_INTB			2			// PCI INTB
+#define CS_PCI_INTC			3			// PCI INTC
+#define CS_PCI_INTD			4			// PCI INTD
+
+// IRQ bitmap reference line	FEDCBA9876543210
+//								0000110000100000b
+#define PCI_IRQ					0xc20	// PCI allowed IRQs here
+
+const struct irq_routing_table intel_irq_routing_table = 
+{
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*6,		/* there can be total 2 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0x0800,			/* IRQs devoted exclusively to PCI usage */
+	0x1022,			/* Vendor */
+	0x208f,			/* Device */
+	0x00000000,		/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xdf,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		// Geode GX3 Host Bridge and VGA Graphics
+		{0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+		// Realtek RTL8100/8139 Network Controller
+		{0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
+		// Reserved for future extensions
+		{0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
+		// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
+		{0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+		// Reserved for future extensions
+		{0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
+		// Reserved for future extensions
+		{0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+        return copy_pirq_routing_table(addr);
+}