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authorStefan Reinauer <stepan@coresystems.de>2010-02-25 18:23:23 +0000
committerStefan Reinauer <stepan@openbios.org>2010-02-25 18:23:23 +0000
commit2e694eda333df2e9a2855d27b0548ec255b9e1a3 (patch)
tree4b61707d2300fe9664b71c6d989f9984d4381921 /src/mainboard/digitallogic
parenteb49f9d04fd19114787c85c173a083574d13fece (diff)
downloadcoreboot-2e694eda333df2e9a2855d27b0548ec255b9e1a3.tar.xz
Drop i855pm port and rename i855gme to i855 instead.
This patch also changes the digitallogic/adl855pc to use that port. It probably won't work, but at least we will get an error if something breaks compilation of the i855 code that is there. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/digitallogic')
-rw-r--r--src/mainboard/digitallogic/adl855pc/Kconfig2
-rw-r--r--src/mainboard/digitallogic/adl855pc/devicetree.cb2
-rw-r--r--src/mainboard/digitallogic/adl855pc/romstage.c8
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig
index 2d99128d18..fd109e9d64 100644
--- a/src/mainboard/digitallogic/adl855pc/Kconfig
+++ b/src/mainboard/digitallogic/adl855pc/Kconfig
@@ -2,7 +2,7 @@ config BOARD_DIGITALLOGIC_ADL855PC
bool "smartModule855"
select ARCH_X86
select CPU_INTEL_SOCKET_MPGA479M
- select NORTHBRIDGE_INTEL_I855PM
+ select NORTHBRIDGE_INTEL_I855
select SOUTHBRIDGE_INTEL_I82801DBM
select SUPERIO_WINBOND_W83627HF
select ROMCC
diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb
index f0106b0648..0f600ac8f1 100644
--- a/src/mainboard/digitallogic/adl855pc/devicetree.cb
+++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb
@@ -1,4 +1,4 @@
-chip northbridge/intel/i855pm
+chip northbridge/intel/i855
device pci_domain 0 on
device pci 0.0 on end
device pci 1.0 on end
diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index cbd8bb0488..16d9195d38 100644
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -17,7 +17,7 @@
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
-#include "northbridge/intel/i855pm/raminit.h"
+#include "northbridge/intel/i855/raminit.h"
#if 0
#include "cpu/p6/apic_timer.c"
@@ -25,7 +25,7 @@
#endif
#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/i855pm/debug.c"
+#include "northbridge/intel/i855/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@@ -57,8 +57,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-#include "northbridge/intel/i855pm/raminit.c"
-#include "northbridge/intel/i855pm/reset_test.c"
+#include "northbridge/intel/i855/raminit.c"
+#include "northbridge/intel/i855/reset_test.c"
#include "lib/generic_sdram.c"
static void main(unsigned long bist)