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authorEric Biederman <ebiederm@xmission.com>2004-10-27 08:53:57 +0000
committerEric Biederman <ebiederm@xmission.com>2004-10-27 08:53:57 +0000
commit6e53f50082cfac4ec2d06d2ff6515781190ad1c0 (patch)
treec352bf640df56343a303c5e5d04042ae2f90ebc8 /src/mainboard/digitallogic
parent20fc678d65b4cdf6b24bdff45ef04933c538e2e8 (diff)
downloadcoreboot-6e53f50082cfac4ec2d06d2ff6515781190ad1c0.tar.xz
sizeram removal/conversion.
- mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/digitallogic')
-rw-r--r--src/mainboard/digitallogic/adl855pc/Config.lb124
1 files changed, 66 insertions, 58 deletions
diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb
index fb2ba53ba4..9871632bfb 100644
--- a/src/mainboard/digitallogic/adl855pc/Config.lb
+++ b/src/mainboard/digitallogic/adl855pc/Config.lb
@@ -202,9 +202,12 @@ end
##
## Setup RAM
##
-mainboardinit cpu/p6/enable_mmx_sse.inc
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/emable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/p6/disable_mmx_sse.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -212,61 +215,66 @@ mainboardinit cpu/p6/disable_mmx_sse.inc
dir /pc80
config chip.h
-northbridge intel/i855pm "i855pm"
-# pci 0:0.0
-# pci 0:1.0
- southbridge intel/i82801dbm "i82801dbm"
-# pci 0:11.0
-# pci 0:11.1
-# pci 0:11.2
-# pci 0:11.3
-# pci 0:11.4
-# pci 0:11.5
-# pci 0:11.6
-# pci 0:12.0
- register "enable_usb" = "0"
- register "enable_native_ide" = "0"
- register "enable_usb" = "0"
- register "enable_native_ide" = "0"
- superio winbond/w83627hf link 1
- pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- register "com1" = "{1}"
- # register "com1" = "{1, 0, 0x3f8, 4}"
- # register "lpt" = "{1}"
- end
+## This does not look right but it is a literal conversion of the
+## old version of this file.
+chip northbridge/intel/i855pm
+ device pci_domain 0 on
+ device pci 0.0 on end
+ device pci 1.0 on end
+ chip southbridge/intel/i82801dbm
+# pci 11.0 on end
+# pci 11.1 on end
+# pci 11.2 on end
+# pci 11.3 on end
+# pci 11.4 on end
+# pci 11.5 on end
+# pci 11.6 on end
+# pci 12.0 on end
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ chip superio/winbond/w83627hf # link 1
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ register "com1" = "{1}"
+ # register "com1" = "{1, 0, 0x3f8, 4}"
+ # register "lpt" = "{1}"
+ end
+ end
+ end
+ device apic_cluster 0 on
+ device cpu/intel/socket_mPGA479M
+ apic 0
+ end
end
end
-
-cpu p6 "cpu0"
-
-end
-
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc