janitor task: unify and cleanup naming.

cache_as_ram_auto.c and auto.c are both called "romstage.c" now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 4 insertions, 142 deletions

diff --git a/src/mainboard/digitallogic/adl855pc/auto.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index cbd8bb0488..cbd8bb0488 100644
--- a/src/mainboard/digitallogic/adl855pc/auto.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
diff --git a/src/mainboard/digitallogic/msm586seg/auto.c b/src/mainboard/digitallogic/msm586seg/romstage.c
index 8f1756b999..8f1756b999 100644
--- a/src/mainboard/digitallogic/msm586seg/auto.c
+++ b/src/mainboard/digitallogic/msm586seg/romstage.c
diff --git a/src/mainboard/digitallogic/msm800sev/Makefile.inc b/src/mainboard/digitallogic/msm800sev/Makefile.inc
index f101f22d4e..0e4b263223 100644
--- a/src/mainboard/digitallogic/msm800sev/Makefile.inc
+++ b/src/mainboard/digitallogic/msm800sev/Makefile.inc
@@ -12,7 +12,7 @@ crt0s += $(src)/cpu/x86/32bit/entry32.inc
 crt0s += $(src)/cpu/x86/16bit/reset16.inc
 crt0s += $(src)/arch/i386/lib/id.inc
 crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc
-crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 
 ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscripts += $(src)/cpu/x86/16bit/entry16.lds
@@ -22,8 +22,8 @@ ldscripts += $(src)/arch/i386/lib/failover.lds
 
 ifdef POST_EVALUATION
 
-$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/build.h
-	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
 	perl -e 's/\.rodata/.rom.data/g' -pi $@
 	perl -e 's/\.text/.section .rom.text/g' -pi $@
 
diff --git a/src/mainboard/digitallogic/msm800sev/auto.c b/src/mainboard/digitallogic/msm800sev/auto.c
deleted file mode 100644
index 29a5661d85..0000000000
--- a/src/mainboard/digitallogic/msm800sev/auto.c
+++ /dev/null
@@ -1,138 +0,0 @@
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
-//#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/lxdef.h>
-
-//#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-        return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/raminit.h"
-
-static inline unsigned int fls(unsigned int x)
-{
-        int r;
-
-        __asm__("bsfl %1,%0\n\t"
-                "jnz 1f\n\t"
-                "movl $32,%0\n"
-                "1:" : "=r" (r) : "g" (x));
-        return r;
-}
-
-
-
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
-{
-	/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
-	 *                      component Banks (byte 17) * module banks, side (byte 5) *
-	 *                      width in bits (byte 6,7)
-	 *                    = Density per side (byte 31) * number of sides (byte 5) */
-	/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
-	msr_t msr;
-	unsigned char module_banks, val;
-
-	
-	msr.hi = 0x10075012;
-	msr.lo = 0x00000040;
-	
-	wrmsr(MC_CF07_DATA, msr);		//GX3
-
-	/* timing and mode ... */
-
-	//msr = rdmsr(0x20000019);
-	
-	/* per standard bios settings */	
-/*
-	msr.hi = 0x18000108;
-	msr.lo = 
-			(6<<28) |		// cas_lat
-			(10<<24)|		// ref2act
-			(7<<20)|		// act2pre
-			(3<<16)|		// pre2act
-			(3<<12)|		// act2cmd
-			(2<<8)|			// act2act
-			(2<<6)|			// dplwr
-			(2<<4)|			// dplrd
-			(3);			// dal
-	* the msr value reported by quanta is very, very different. 
-	 * we will go with that value for now. 
-	 *
-	//msr.lo = 0x286332a3;
-*/
-	//wrmsr(0x20000019, msr);	//GX3
-
-}
-
-#include "northbridge/amd/lx/raminit.c"
-#include "lib/generic_sdram.c"
-
-/* CPU and GLIU mult/div */
-#define PLLMSRhi 0x0000039C
-/* Hold Count - how long we will sit in reset */
-#define PLLMSRlo 0x00DE0000
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-static void msr_init(void)
-{
-
-	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
-        __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-}
-
-	
-static void main(unsigned long bist)
-{
-	static const struct mem_controller memctrl [] = {
-		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
-	};
-
-	SystemPreInit();			//GX3 OK
-
-	msr_init();					//GX3 OK
-
-	cs5536_early_setup();		//GX3 OK
-
-	/* NOTE: must do this AFTER the early_setup!
-	 * it is counting on some early MSR setup
-	 * for cs5536
-	 */
-	cs5536_setup_onchipuart();	//GX3 OK
-
-	uart_init();				//GX3 OK
-	console_init();				//GX3 OK
-
-	pll_reset();				//GX3 OK
-
-	cpuRegInit();				//GX3 OK
-
-	print_err("done cpuRegInit\n");
-	
-	sdram_initialize(1, memctrl);	//GX3 OK almost
-	
-	/* Check all of memory */
-	//ram_check(0x00000000, 640*1024);
-}
diff --git a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 70fa935a8d..03f9fae57b 100644
--- a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(void)
 
 	/* Switch from Cache as RAM to real RAM */
 	/* There are two ways we could think about this.
-	 1. If we are using the auto.inc ROMCC way, the stack is going to be re-setup in the code following this code.
+	 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
 		Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
 	 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
 		That means we care about what is in the stack. If we are smart we set the CAR stack to the same location