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| author | Andrew Wu <arw@dmp.com.tw> | 2013-10-25 16:22:57 +0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-11-24 05:36:36 +0100 |
| commit | 33b09567d291d3e07429c94e38ec6210435c42c1 (patch) | |
| tree | b56de4af909023ab57805357b363b5e8ab52536e /src/mainboard/dmp | |
| parent | 099b914dcd63cb8c177fa1e981046cd25f4565f7 (diff) | |
| download | coreboot-33b09567d291d3e07429c94e38ec6210435c42c1.tar.xz | |
dmp/vortex86ex: Move DMP specific POST code defines into one file
Move into src/cpu/dmp/dmp_post_code.h
Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3989
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/dmp')
| -rw-r--r-- | src/mainboard/dmp/vortex86ex/romstage.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index 72fbde08e5..b08d621e75 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -27,6 +27,7 @@ #include "northbridge/dmp/vortex86ex/northbridge.h" #include "southbridge/dmp/vortex86ex/southbridge.h" #include "northbridge/dmp/vortex86ex/raminit.c" +#include "cpu/dmp/dmp_post_code.h" #define DMP_CPUID_SX 0x31504d44 #define DMP_CPUID_DX 0x32504d44 @@ -35,11 +36,6 @@ #define DMP_CPUID_MX_PLUS 0x35504d44 #define DMP_CPUID_EX 0x37504d44 -/* Post codes */ -#define POST_DMP_ID_ERR 0x85 -#define POST_DRAM_TEST_ERR 0x86 -#define POST_DRAM_SIZING_ERR 0x77 - static u32 get_dmp_id(void) { return pci_read_config32(NB, NB_REG_CID); @@ -273,7 +269,7 @@ static void test_dram_stability(void) } } if (v != -1) { - post_code(POST_DRAM_TEST_ERR); + post_code(POST_DMP_DRAM_TEST_ERR); print_emerg("DRAM stablility test error!\nADDR = "); print_emerg_hex32(v); print_emerg(", WRITE = "); @@ -342,7 +338,7 @@ static void main(unsigned long bist) reg_nb_f1_cc &= ~(1 << 4); pci_write_config8(NB1, 0xcc, reg_nb_f1_cc); if (detect_ddr3_dram_size()) { - post_code(POST_DRAM_SIZING_ERR); + post_code(POST_DMP_DRAM_SIZING_ERR); die("DRAM sizing error!\n"); } /* Reset enhance read push write to default(enable) */ |