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author | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:04:01 +0000 |
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committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:04:01 +0000 |
commit | 4e83d70a4393674ac3b54d1343533fc1d2c489d0 (patch) | |
tree | 8bd72bfeec029eedd692a88aa5c401ce9ace66ad /src/mainboard/eaglelion/5bcm/auto.c | |
parent | b47a4d3347972704cc05b1a55c0af582764815aa (diff) | |
download | coreboot-4e83d70a4393674ac3b54d1343533fc1d2c489d0.tar.xz |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-25
Creator: Hamish Guthrie <hamish@prodigi.ch>
Adds a tree for the Eaglelion mainboard. This board has an AMD GX1 processor in a typical Mini-ATX format with a few ISA and PCI slots.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/eaglelion/5bcm/auto.c')
-rw-r--r-- | src/mainboard/eaglelion/5bcm/auto.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/mainboard/eaglelion/5bcm/auto.c b/src/mainboard/eaglelion/5bcm/auto.c new file mode 100644 index 0000000000..cefa559ffe --- /dev/null +++ b/src/mainboard/eaglelion/5bcm/auto.c @@ -0,0 +1,55 @@ +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +//#include "southbridge/intel/i440bx/i440bx_early_smbus.c" +#include "superio/NSC/pc97317/pc97317_early_serial.c" +//#include "northbridge/intel/i440bx/raminit.h" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) + +//#include "debug.c" +//#include "lib/delay.c" + +#include "northbridge/amd/gx1/raminit.c" + +static void main(unsigned long bist) +{ + pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + sdram_init(); + + /* Check all of memory */ +#if 0 + ram_check(0x00000000, msr.lo); +#endif +#if 0 + static const struct { + unsigned long lo, hi; + } check_addrs[] = { + /* Check 16MB of memory @ 0*/ + { 0x00000000, 0x01000000 }, +#if TOTAL_CPUS > 1 + /* Check 16MB of memory @ 2GB */ + { 0x80000000, 0x81000000 }, +#endif + }; + int i; + for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + ram_check(check_addrs[i].lo, check_addrs[i].hi); + } +#endif +} |