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authorNikolay Petukhov <nikolay.petukhov@gmail.com>2008-03-29 16:59:27 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-03-29 16:59:27 +0000
commit9c2255c66c20cd90f39cc08c1220d93222d5d580 (patch)
tree5856ba073775b3259a454545d7b6a3fda4c82824 /src/mainboard/eaglelion
parent0e122af46553c394b1ac4c38dd83ab01c7c34a9c (diff)
downloadcoreboot-9c2255c66c20cd90f39cc08c1220d93222d5d580.tar.xz
Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch] for the right IRQ setup. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p. I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add IRQ routing for AMD/GX1 boards in coreboot. The pirq.patch for IRQ routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign IRQ for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.patch depends of type chipset and set PIRQx lines in interrupt router. This part supports only CS5530/5536 interrupt routers. IRQ routing functionality is included through PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020, see http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/eaglelion')
-rw-r--r--src/mainboard/eaglelion/5bcm/Options.lb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb
index 280f582845..c10b7b9cc0 100644
--- a/src/mainboard/eaglelion/5bcm/Options.lb
+++ b/src/mainboard/eaglelion/5bcm/Options.lb
@@ -42,6 +42,7 @@ uses TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -75,6 +76,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=2
+default PIRQ_ROUTE=1
#object irq_tables.o
##