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| author | Anders Jenbo <anders@jenbo.dk> | 2010-06-09 08:08:12 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-06-09 08:08:12 +0000 |
| commit | a06f950c27651d82e2e1b95fa2690a3cab70750b (patch) | |
| tree | 9b5752caf9a4c3c18e1921613d33b5f3f29f3f96 /src/mainboard/ecs/p6iwp-fe/Kconfig | |
| parent | bd8d7eed2d4ded65ebd3ecc0f9300e8eba822068 (diff) | |
| download | coreboot-a06f950c27651d82e2e1b95fa2690a3cab70750b.tar.xz | |
This patch adds the ECS P6IWP-Fe board to coreboot.
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/ecs/p6iwp-fe/Kconfig')
| -rw-r--r-- | src/mainboard/ecs/p6iwp-fe/Kconfig | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig new file mode 100644 index 0000000000..d2129a8d21 --- /dev/null +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ECS_P6IWP_FE + bool "P6IWP-FE" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801AX + select SUPERIO_ITE_IT8712F + select ROMCC + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default ecs/p6iwp-fe + depends on BOARD_ECS_P6IWP_FE + +config MAINBOARD_PART_NUMBER + string + default "P6IWP-FE" + depends on BOARD_ECS_P6IWP_FE + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ECS_P6IWP_FE + +config IRQ_SLOT_COUNT + int + default 10 + depends on BOARD_ECS_P6IWP_FE + |