diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-24 13:33:45 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-13 00:46:55 +0100 |
| commit | e3fd63f264e1f6e2869cf5868e1810dff5641147 (patch) | |
| tree | 8c47722ba432db52850738723567547ad555b956 /src/mainboard/ecs | |
| parent | 63db6142b6198fc3d6660e58228eeedd2eac59bd (diff) | |
| download | coreboot-e3fd63f264e1f6e2869cf5868e1810dff5641147.tar.xz | |
northbridge/intel/i82810: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i810 boards in the chipset.
Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/ecs')
| -rw-r--r-- | src/mainboard/ecs/p6iwp-fe/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/ecs/p6iwp-fe/romstage.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index 9098362725..9afae9a039 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_ITE_IT8712F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 73176e8e0e..3e8a0843f6 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> |