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| author | Yuichi Ito <yui.corebt@gmail.com> | 2016-07-28 13:34:18 +0900 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-09-29 15:55:15 +0200 |
| commit | b31c3d1b921e45d26a2fdade45e82ca3a8af5c74 (patch) | |
| tree | eb0dad555cda99d8f2a63e7de0c1932100367a33 /src/mainboard/elmex/pcm205400/dsdt.asl | |
| parent | fa74e4705dbb5ecf5ba466fd6a9bc309f7e3e8bf (diff) | |
| download | coreboot-b31c3d1b921e45d26a2fdade45e82ca3a8af5c74.tar.xz | |
src/mainboard: Add vendor ELMEX with a board
Add board with amd/persimmon as template.
Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67
Signed-off-by: Yuichi Ito <yui.corebt@gmail.com>
Reviewed-on: https://review.coreboot.org/15926
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/elmex/pcm205400/dsdt.asl')
| -rw-r--r-- | src/mainboard/elmex/pcm205400/dsdt.asl | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl new file mode 100644 index 0000000000..0cf657f23a --- /dev/null +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" +} +/* End of ASL file */ |