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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-30 17:46:17 +0200
committerMartin Roth <martinroth@google.com>2016-08-14 19:06:25 +0200
commit8ab989e31561cea0c6af5d5e242dd2be97bc73b4 (patch)
tree31bc3a2175762b179d2fc093c34f62c18b15b9ee /src/mainboard/emulation/qemu-i440fx
parent589ef9de8faa2db11a7ce2769fc1d9396a82886b (diff)
downloadcoreboot-8ab989e31561cea0c6af5d5e242dd2be97bc73b4.tar.xz
src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-i440fx')
-rw-r--r--src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl4
-rw-r--r--src/mainboard/emulation/qemu-i440fx/fw_cfg.c18
-rw-r--r--src/mainboard/emulation/qemu-i440fx/northbridge.c4
3 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
index 0f3e83b14d..17e166ce36 100644
--- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
+++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
@@ -43,7 +43,7 @@ Scope(\_SB) {
PRS, 256
}
Method(PRSC, 0) {
- // Local5 = active cpu bitmap
+ // Local5 = active CPU bitmap
Store(PRS, Local5)
// Local2 = last read byte from bitmap
Store(Zero, Local2)
@@ -56,7 +56,7 @@ Scope(\_SB) {
// Shift down previously read bitmap byte
ShiftRight(Local2, 1, Local2)
} Else {
- // Read next byte from cpu bitmap
+ // Read next byte from CPU bitmap
Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
}
// Local3 = active state for this cpu
diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
index 9f6a55ce97..565b85585c 100644
--- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
+++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
@@ -118,21 +118,21 @@ int fw_cfg_max_cpus(void)
/* ---------------------------------------------------------------------- */
/*
- * Starting with release 1.7 qemu provides acpi tables via fw_cfg.
+ * Starting with release 1.7 qemu provides ACPI tables via fw_cfg.
* Main advantage is that new (virtual) hardware which needs acpi
* support JustWorks[tm] without having to patch & update the firmware
* (seabios, coreboot, ...) accordingly.
*
* Qemu provides a etc/table-loader file with instructions for the
* firmware:
- * - A "load" instruction to fetch acpi data from fw_cfg.
+ * - A "load" instruction to fetch ACPI data from fw_cfg.
* - A "pointer" instruction to patch a pointer. This is needed to
* get table-to-table references right, it is basically a
- * primitive dynamic linker for acpi tables.
- * - A "checksum" instruction to generate acpi table checksums.
+ * primitive dynamic linker for ACPI tables.
+ * - A "checksum" instruction to generate ACPI table checksums.
*
* If a etc/table-loader file is found we'll go try loading the acpi
- * tables from fw_cfg, otherwise we'll fallback to the acpi tables
+ * tables from fw_cfg, otherwise we'll fallback to the ACPI tables
* compiled in.
*/
@@ -211,7 +211,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
if (rc < 0)
return 0;
- printk(BIOS_DEBUG, "QEMU: found acpi tables in fw_cfg.\n");
+ printk(BIOS_DEBUG, "QEMU: found ACPI tables in fw_cfg.\n");
max = rc / sizeof(*s);
s = malloc(rc);
@@ -259,7 +259,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
default:
/*
- * Should not happen. acpi knows 1 and 2 byte ptrs
+ * Should not happen. ACPI knows 1 and 2 byte ptrs
* too, but we are operating with 32bit offsets which
* would simply not fit in there ...
*/
@@ -293,13 +293,13 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
};
}
- printk(BIOS_DEBUG, "QEMU: loaded acpi tables from fw_cfg.\n");
+ printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n");
free(s);
free(addrs);
return ALIGN(current, 16);
err:
- printk(BIOS_DEBUG, "QEMU: loading acpi tables from fw_cfg failed.\n");
+ printk(BIOS_DEBUG, "QEMU: loading ACPI tables from fw_cfg failed.\n");
free(s);
free(addrs);
return 0;
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 26cbda5a6b..575069cc7e 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -72,7 +72,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
fw_cfg_load_file("etc/e820", list);
for (i = 0; i < size/sizeof(*list); i++) {
switch (list[i].type) {
- case 1: /* ram */
+ case 1: /* RAM */
printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
if (list[i].address == 0) {
@@ -135,7 +135,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
* Reserve the region between top-of-ram and the
* mmconf xbar (ar 0xb0000000), so coreboot doesn't
* place pci bars there. The region isn't declared as
- * pci io window in the acpi tables (\_SB.PCI0._CRS).
+ * pci io window in the ACPI tables (\_SB.PCI0._CRS).
*/
res = new_resource(dev, idx++);
res->base = tomk * 1024;