mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK

Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like
VBOOT with separate verstage.

Changes:
* Use symbols to set up CAR and STACK
* Zero CAR area
* Move BIST failure checking to cpu folder
* Rename functions where necessary

Tested:
* qemu-2.11.2 machine pc
* qemu-2.11.2 machine q35

Test result:
* BIST error reporting is still working.
* Console starts in bootblock
* SeaBios 1.11.2 as payload is still working

Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 25 insertions, 1 deletions

diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 3625cf903a..2125bd1db3 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -12,6 +12,8 @@
  */
 
 #include <arch/io.h>
+#include <bootblock_common.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
 
 /* Just define these here, there is no gm35.h file to include. */
 #define D0F0_PCIEXBAR_LO 0x60
@@ -39,7 +41,29 @@ static void bootblock_northbridge_init(void)
 	pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
 }
 
-static void bootblock_mainboard_init(void)
+static void enable_spi_prefetch(void)
+{
+	u8 reg8;
+	pci_devfn_t dev;
+
+	dev = PCI_DEV(0, 0x1f, 0);
+
+	reg8 = pci_read_config8(dev, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void bootblock_southbridge_init(void)
+{
+	enable_spi_prefetch();
+
+	/* Enable RCBA */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
+			(uintptr_t)DEFAULT_RCBA | 1);
+}
+
+void bootblock_soc_init(void)
 {
 	bootblock_northbridge_init();
 	bootblock_southbridge_init();