diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-01-07 13:21:22 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-08 23:33:35 +0100 |
| commit | 597ff87574b11dc1163eb152e0941a2cbce5341b (patch) | |
| tree | 3205d41368b0bd2a1936c795d668b43761292872 /src/mainboard/emulation/qemu-x86/Kconfig | |
| parent | c01990789f533316e10c5fc3b5ca08ae866b8033 (diff) | |
| download | coreboot-597ff87574b11dc1163eb152e0941a2cbce5341b.tar.xz | |
qemu-x86: Implement more features
This patch switches the Qemu target to use (pseudo) Cache As RAM
and enables some ACPI code. This allows to use the CBMEM console
and timestamp code with coreboot in Qemu. Right now, the ACPI code
is commented out because leaving it in breaks IDE.
Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2113
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-x86/Kconfig')
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/Kconfig | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/emulation/qemu-x86/Kconfig b/src/mainboard/emulation/qemu-x86/Kconfig index db1a0270b8..c171309799 100644 --- a/src/mainboard/emulation/qemu-x86/Kconfig +++ b/src/mainboard/emulation/qemu-x86/Kconfig @@ -4,9 +4,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select SOUTHBRIDGE_INTEL_I82371EB - select ROMCC + select CACHE_AS_RAM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR @@ -21,4 +23,13 @@ config IRQ_SLOT_COUNT int default 6 +config DCACHE_RAM_BASE + hex + default 0xd0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + + endif # BOARD_EMULATION_QEMU_X86 |