mb/emulation/spike-riscv: Implement mtime_init

This patch lets spike boot to "Payload not loaded" again.

Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy
directory for emulators, and different emulators might have different
memory maps, I moved mtime_init to the mainboard-specific directories
for Spike and QEMU.

Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc
index 36f1fca58c..38977b6345 100644
--- a/src/mainboard/emulation/spike-riscv/Makefile.inc
+++ b/src/mainboard/emulation/spike-riscv/Makefile.inc
@@ -14,11 +14,13 @@
 
 bootblock-y += uart.c
 bootblock-y += rom_media.c
+bootblock-y += clint.c
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
 ramstage-y += uart.c
 ramstage-y += rom_media.c
+ramstage-y += clint.c
 
 bootblock-y += memlayout.ld
 romstage-y += memlayout.ld