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author | Philipp Hug <philipp@hug.cx> | 2019-09-04 09:24:45 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-06 15:09:48 +0000 |
commit | 934ae21b52492c9c730dc5accd2900b32c5c1492 (patch) | |
tree | e8fecc91580592ac857326077ce9c486e31af017 /src/mainboard/emulation/spike-riscv/clint.c | |
parent | 8cb5ea7879cf82b79ab9a2c4342c542a167943bf (diff) | |
download | coreboot-934ae21b52492c9c730dc5accd2900b32c5c1492.tar.xz |
mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
TEST=Set MAX_CPUS=2 and run qemu with -smp 2
Signed-off-by: Philipp Hug <philipp@hug.cx>
Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv/clint.c')
-rw-r--r-- | src/mainboard/emulation/spike-riscv/clint.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 7ad3f5a7af..c39e05831c 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -14,6 +14,7 @@ */ #include <mcall.h> +#include <device/mmio.h> #define SPIKE_CLINT_BASE 0x02000000 @@ -24,3 +25,8 @@ void mtime_init(void) HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); +} |