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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-10-28 00:25:02 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2016-11-07 16:47:49 +0100 |
| commit | 99f2f113ec397dd042dcaa23c47123f3def19ebc (patch) | |
| tree | 38b8eb7e1ad90c2d5e2b2bb6ed32ddca99016214 /src/mainboard/emulation/spike-riscv/uart.c | |
| parent | 7ca9b8ae5014a745855296903682ae803235cb35 (diff) | |
| download | coreboot-99f2f113ec397dd042dcaa23c47123f3def19ebc.tar.xz | |
riscv: Unify SBI call implementations under arch/riscv/
Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.
TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
payload. It worked as much as before (Linux didn't boot, but it
made some successful SBI calls)
Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv/uart.c')
| -rw-r--r-- | src/mainboard/emulation/spike-riscv/uart.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 8513849f05..57647fee1d 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -17,7 +17,6 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> -#include <spike_util.h> uintptr_t uart_platform_base(int idx) { |