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| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-10-19 17:29:23 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-05 13:35:59 +0000 |
| commit | 0688ab8d95f18f718510cc17aeb01a47519a9a5a (patch) | |
| tree | 05fcd7af442ef1f32e85b34d1cdf5ac25371d434 /src/mainboard/emulation/spike-riscv | |
| parent | 3a065f1a76feb4f23af6708caef5f912292610fd (diff) | |
| download | coreboot-0688ab8d95f18f718510cc17aeb01a47519a9a5a.tar.xz | |
google/kukui: Support TPM
Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ,
implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM
interrupt.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui.
Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions