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authorRonald G. Minnich <rminnich@gmail.com>2016-11-06 20:54:20 -0800
committerRonald G. Minnich <rminnich@gmail.com>2016-11-12 19:23:22 +0100
commit574df1ba670aaac265ba44b2c94e831dfff9f96d (patch)
tree229c0ab937fbee26b1c8c8c79b5c105afae06204 /src/mainboard/emulation/spike-riscv
parent04c94ded3a1b4143c3186321a95c547af5377d99 (diff)
downloadcoreboot-574df1ba670aaac265ba44b2c94e831dfff9f96d.tar.xz
riscv: start to use the configstring functions
These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Define a new config variable, CONFIG_RISCV_CONFIGSTRING, which has a default value that works on all existing systems but which can be changed as needed for a new SOC or mainboard. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17256 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
-rw-r--r--src/mainboard/emulation/spike-riscv/romstage.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv/romstage.c
index b6314ccd1c..dccdf226fb 100644
--- a/src/mainboard/emulation/spike-riscv/romstage.c
+++ b/src/mainboard/emulation/spike-riscv/romstage.c
@@ -15,9 +15,15 @@
#include <console/console.h>
#include <program_loading.h>
+#include <commonlib/configstring.h>
void main(void)
{
+ uintptr_t base;
+ size_t size;
+
console_init();
+ query_mem(configstring(), &base, &size);
+ printk(BIOS_SPEW, "0x%zx bytes of memory at 0x%llx\n", size, base);
run_ramstage();
}