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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2017-09-26 01:44:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-11-07 12:30:38 +0000 |
| commit | 5a6e389747d37e4ed69d9261187155c83739a649 (patch) | |
| tree | 2fe954449bb7a0db759f6e532a766ebef61d9e12 /src/mainboard/emulation/spike-riscv | |
| parent | c90f1d7be0bb41e1e74b5a6f7c4ceb4a2fceada8 (diff) | |
| download | coreboot-5a6e389747d37e4ed69d9261187155c83739a649.tar.xz | |
arch/riscv: Use a separate trap stack
This is the lazy solution, as explained in the comment, but it works for
now.
Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions