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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-06-10 19:35:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:11:49 +0200 |
| commit | 710566093a504f0fecb641661c5379cad268189b (patch) | |
| tree | 3707b8c91b624e0e4dd40653d46674200eb03dc6 /src/mainboard/emulation | |
| parent | 2459f677310efdde229bab3406b2fb5d91f5ec20 (diff) | |
| download | coreboot-710566093a504f0fecb641661c5379cad268189b.tar.xz | |
riscv-spike: Move coreboot to 0x80000000 (2GiB)
This is where the RAM is (now), on RISC-V.
We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.
Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/emulation')
| -rw-r--r-- | src/mainboard/emulation/spike-riscv/memlayout.ld | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 276483f336..8d35a64a9c 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -17,12 +17,14 @@ #include <arch/header.ld> +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - STACK(8M, 64K) - ROMSTAGE(8M + 64K, 128K) - PRERAM_CBMEM_CONSOLE(8M + 192k, 8K) - RAMSTAGE(8M + 200K, 256K) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + RAMSTAGE(START + 8M + 200K, 256K) } |