diff options
| author | Gerd Hoffmann <kraxel@redhat.com> | 2013-06-17 13:30:50 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-17 16:59:14 +0200 |
| commit | 44b11f2fe423a04641ca1059d2ba5a188412cdc7 (patch) | |
| tree | 6b8208587d5a7545637e81348c1cb7ebff23e8f1 /src/mainboard/emulation | |
| parent | 156ff1304905845736834d33b6a2d04ef5773ec5 (diff) | |
| download | coreboot-44b11f2fe423a04641ca1059d2ba5a188412cdc7.tar.xz | |
qemu: move ram ressource reservation from "set" to "read" stage
So the pci allocation code knows where memory is and doesn't
try map pci devices there. We also don't have to check for
overlaps between pci hole and memory then.
Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3491
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation')
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/northbridge.c | 34 |
1 files changed, 12 insertions, 22 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index c2e4ba22b3..ed372b6a9f 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -18,39 +18,29 @@ static void cpu_pci_domain_set_resources(device_t dev) { - u32 pci_tolm = find_pci_tolm(dev->link_list); - unsigned long tomk = 0, tolmk; - int idx; + assign_resources(dev->link_list); +} + +static void cpu_pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + unsigned long tomk = 0; + int idx = 10; + + pci_domain_read_resources(dev); tomk = qemu_get_memory_size(); - printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", - tomk, tomk / 1024); - - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does not overlap the memory. */ - tolmk = tomk; - } + printk(BIOS_DEBUG, "Detected %lu MiB RAM.\n", tomk / 1024); /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); + ram_resource(dev, idx++, 768, tomk - 768); /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; - assign_resources(dev->link_list); -} - -static void cpu_pci_domain_read_resources(struct device *dev) -{ - struct resource *res; - - pci_domain_read_resources(dev); - /* Reserve space for the IOAPIC. This should be in the Southbridge, * but I couldn't tell which device to put it in. */ res = new_resource(dev, 2); |