esd/atom15: import esd atom15 board

This patch adds esd atom15 board with
Intel Atom E3815 SoC.

Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12632
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

17 files changed, 913 insertions, 0 deletions

diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig
new file mode 100644
index 0000000000..3f4b76ba1b
--- /dev/null
+++ b/src/mainboard/esd/atom15/Kconfig
@@ -0,0 +1,70 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+## Copyright (C) 2014 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ESD_ATOM15
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SOC_INTEL_FSP_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select TSC_MONOTONIC_TIMER
+	select HAVE_ACPI_RESUME
+
+config MAINBOARD_DIR
+	string
+	default "esd/atom15"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "esd atom15"
+
+config MAX_CPUS
+	int
+	default 16
+
+config CACHE_ROM_SIZE_OVERRIDE
+	hex
+	default 0x800000
+
+config FSP_FILE
+	string
+	default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
+
+config CBFS_SIZE
+	hex
+	default 0x00300000
+
+config ENABLE_FSP_FAST_BOOT
+	bool
+	depends on HAVE_FSP_BIN
+	default y
+
+config VIRTUAL_ROM_SIZE
+	hex
+	depends on ENABLE_FSP_FAST_BOOT
+	default 0x800000
+
+config POST_DEVICE
+	bool
+	default n
+
+config VGA_BIOS
+	bool
+	default y if FSP_PACKAGE_DEFAULT
+
+endif # BOARD_ESD_ATOM15
diff --git a/src/mainboard/esd/atom15/Kconfig.name b/src/mainboard/esd/atom15/Kconfig.name
new file mode 100644
index 0000000000..cab7e864db
--- /dev/null
+++ b/src/mainboard/esd/atom15/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ESD_ATOM15
+	bool "Atom15"
diff --git a/src/mainboard/esd/atom15/Makefile.inc b/src/mainboard/esd/atom15/Makefile.inc
new file mode 100644
index 0000000000..3074df2138
--- /dev/null
+++ b/src/mainboard/esd/atom15/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += gpio.c
+ramstage-y += irqroute.c
diff --git a/src/mainboard/esd/atom15/acpi/ec.asl b/src/mainboard/esd/atom15/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/esd/atom15/acpi/ec.asl
diff --git a/src/mainboard/esd/atom15/acpi/mainboard.asl b/src/mainboard/esd/atom15/acpi/mainboard.asl
new file mode 100644
index 0000000000..b032ee189d
--- /dev/null
+++ b/src/mainboard/esd/atom15/acpi/mainboard.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+}
diff --git a/src/mainboard/esd/atom15/acpi/superio.asl b/src/mainboard/esd/atom15/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/esd/atom15/acpi/superio.asl
diff --git a/src/mainboard/esd/atom15/acpi_tables.c b/src/mainboard/esd/atom15/acpi_tables.c
new file mode 100644
index 0000000000..48991f5aea
--- /dev/null
+++ b/src/mainboard/esd/atom15/acpi_tables.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h> // hexdump
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <baytrail/acpi.h>
+#include <baytrail/nvs.h>
+#include <baytrail/iomap.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+
+	/* No TPM Present */
+	gnvs->tpmp = 0;
+
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	current = acpi_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/src/mainboard/esd/atom15/board_info.txt b/src/mainboard/esd/atom15/board_info.txt
new file mode 100644
index 0000000000..b5099b325d
--- /dev/null
+++ b/src/mainboard/esd/atom15/board_info.txt
@@ -0,0 +1,4 @@
+Category: sbc
+ROM protocol: SPI
+Flashrom support: y
+Release year: 2015
diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout
new file mode 100644
index 0000000000..8aaa522bb8
--- /dev/null
+++ b/src/mainboard/esd/atom15/cmos.layout
@@ -0,0 +1,116 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+411          2       e       8        use_xhci_over_ehci
+#413          3       r       0        unused
+
+# MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+#save timestamps in pre-ram boot areas
+1719        64       h       0        timestamp_value1
+1783        64       h       0        timestamp_value2
+1847        64       h       0        timestamp_value3
+1911        64       h       0        timestamp_value4
+1975        64       h       0        timestamp_value5
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+8     0     EHCI
+8     1     XHCI
+8     2     Default
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/esd/atom15/devicetree.cb b/src/mainboard/esd/atom15/devicetree.cb
new file mode 100644
index 0000000000..769a687fea
--- /dev/null
+++ b/src/mainboard/esd/atom15/devicetree.cb
@@ -0,0 +1,93 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+## Copyright (C) 2014 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/fsp_baytrail
+
+	#### ACPI Register Settings ####
+	register "fadt_pm_profile"         = "PM_UNSPECIFIED"
+	register "fadt_boot_arch"          = "ACPI_FADT_LEGACY_FREE"
+
+	#### FSP register settings ####
+	register "PcdSataMode"             = "SATA_MODE_AHCI"
+	register "PcdMrcInitSPDAddr1"      = "SPD_ADDR_DEFAULT"
+	register "PcdMrcInitSPDAddr2"      = "SPD_ADDR_DEFAULT"
+	register "PcdMrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
+	register "PcdeMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"
+	register "PcdIgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
+	register "PcdApertureSize"         = "APERTURE_SIZE_DEFAULT"
+	register "PcdGttSize"              = "GTT_SIZE_DEFAULT"
+	register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
+	register "AzaliaAutoEnable"        = "AZALIA_FOLLOWS_DEVICETREE"
+	register "LpeAcpiModeEnable"       = "LPE_ACPI_MODE_DISABLED"
+	register "IgdRenderStandby"        = "IGD_RENDER_STANDBY_ENABLE"
+	register "EnableMemoryDown"        = "MEMORY_DOWN_ENABLE"
+	register "DRAMSpeed"               = "DRAM_SPEED_1066MHZ"
+	register "DRAMType"                = "DRAM_TYPE_DDR3L"
+	register "DIMM0Enable"             = "DIMM0_ENABLE"
+	register "DIMM1Enable"             = "DIMM1_DISABLE"
+	register "DIMMDWidth"              = "DIMM_DWIDTH_X16"
+	register "DIMMDensity"             = "DIMM_DENSITY_4G_BIT"
+	register "DIMMBusWidth"            = "DIMM_BUS_WIDTH_64BIT"
+	register "DIMMSides"               = "DIMM_SIDES_1RANK"
+	register "DIMMtCL"                 = "8"
+	register "DIMMtRPtRCD"             = "8"
+	register "DIMMtWR"                 = "8"
+	register "DIMMtWTR"                = "4"
+	register "DIMMtRRD"                = "6"
+	register "DIMMtRTP"                = "4"
+	register "DIMMtFAW"                = "27"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end	# 8086 0F00 - SoC router		-
+		device pci 02.0 off end	# 8086 0F31 - GFX			-
+		device pci 03.0 off end # 8086 0F38 - MIPI			-
+
+		device pci 10.0 off end	# 8086 0F14 - EMMC Port			-
+		device pci 11.0 off end	# 8086 0F15 - SDIO Port			-
+		device pci 12.0 on end	# 8086 0F16 - SD Port			MicroSD on SD3
+		device pci 13.0 off end	# 8086 0F23 - SATA AHCI			-
+		device pci 14.0 off end	# 8086 0F35 - USB XHCI 			-
+		device pci 15.0 off end	# 8086 0F28 - LP Engine Audio		-
+		device pci 17.0 off end	# 8086 0F50 - MMC Port			-
+		device pci 18.0 on end	# 8086 0F40 - SIO - DMA			-
+		device pci 18.1 on end	# 8086 0F41 -   I2C Port 1 (0)		-
+		device pci 18.2 on end	# 8086 0F42 -   I2C Port 2 (1)		-
+		device pci 18.3 on end	# 8086 0F43 -   I2C Port 3 (2)		-
+		device pci 18.4 on end	# 8086 0F44 -   I2C Port 4 (3)		-
+		device pci 18.5 on end	# 8086 0F45 -   I2C Port 5 (4)		-
+		device pci 18.6 on end	# 8086 0F46 -   I2C Port 6 (5)		EEPROM
+		device pci 18.7 off end	# 8086 0F47 -   I2C Port 7 (6)		-
+		device pci 1a.0 off end	# 8086 0F18 - TXE			-
+		device pci 1b.0 off end	# 8086 0F04 - HD Audio			-
+		device pci 1c.0 on end	# 8086 0F48 - PCIe Port 1 (0)		-
+		device pci 1c.1 off end	# 8086 0F4A - PCIe Port 2 (1)		-
+		device pci 1c.2 on end	# 8086 0F4C - PCIe Port 3 (2)		ETHERNET
+		device pci 1c.3 on end	# 8086 0F4E - PCIe Port 4 (3)		CAN
+		device pci 1d.0 on end	# 8086 0F34 - USB EHCI - Enabling EHCI  -
+		device pci 1e.0 on end	# 8086 0F06 - SIO - DMA			-
+		device pci 1e.1 on end	# 8086 0F08 -   PWM 1			-
+		device pci 1e.2 on end	# 8086 0F09 -   PWM 2			-
+		device pci 1e.3 on end	# 8086 0F0A -   HSUART 1		Alternate uart
+		device pci 1e.4 off end	# 8086 0F0C -   HSUART 2		-
+		device pci 1e.5 off end	# 8086 0F0E -   SPI			-
+		device pci 1f.0 on end	# 8086 0F1C - LPC bridge		No connector
+		device pci 1f.3 on end	# 8086 0F12 - SMBus 0			SPC
+	end
+end
diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl
new file mode 100644
index 0000000000..63b9d03dbb
--- /dev/null
+++ b/src/mainboard/esd/atom15/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define INCLUDE_LPE  1
+#define INCLUDE_SCC  1
+#define INCLUDE_EHCI 1
+#define INCLUDE_XHCI 1
+#define INCLUDE_LPSS 1
+
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include <soc/intel/fsp_baytrail/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
+
+	#include <soc/intel/fsp_baytrail/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/fsp_baytrail/acpi/sleepstates.asl>
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/esd/atom15/fadt.c b/src/mainboard/esd/atom15/fadt.c
new file mode 100644
index 0000000000..38b9bfdd3f
--- /dev/null
+++ b/src/mainboard/esd/atom15/fadt.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baytrail/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	acpi_fill_in_fadt(fadt,facs,dsdt);
+
+	/* Platform specific customizations go here */
+
+	header->checksum = 0;
+	header->checksum =
+		acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+
+}
diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c
new file mode 100644
index 0000000000..f617de48ef
--- /dev/null
+++ b/src/mainboard/esd/atom15/gpio.c
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <baytrail/gpio.h>
+#include "irqroute.h"
+
+/*
+ * For multiplexed functions, look in EDS:
+ * 10.3 Ball Name and Function by Location
+ *
+ * The pads list is in the BWG_VOL2 Rev1p2:
+ * Note that Pad # is not the same as GPIO#
+ * 37 GPIO Handling:
+ *  Table 37-1. SCORE Pads List
+ *  Table 37-2. SSUSORE Pads List
+ */
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,				/* GPIO_S0_NC[00] - HDMI_HPD */
+	GPIO_FUNC2,				/* GPIO_S0_NC[01] - HDMI_DDCDAT */
+	GPIO_FUNC2,				/* GPIO_S0_NC[02] - HDMI_DDCCLK */
+	GPIO_NC,				/* GPIO_S0_NC[03] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[04] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[05] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[06] - No Connect */
+	GPIO_FUNC2,				/* GPIO_S0_NC[07] - DDI1_DDCDAT */
+	GPIO_NC,				/* GPIO_S0_NC[08] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[09] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[10] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[11] - No Connect */
+	GPIO_FUNC(0, PULL_UP, 20K),		/* GPIO_S0_NC[12] - TP15 */
+	GPIO_NC,				/* GPIO_S0_NC[13] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[14] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[15] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[16] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[17] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[18] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[19] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[20] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[21] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[22] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[23] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[24] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[25] - No Connect */
+	GPIO_NC,				/* GPIO_S0_NC[26] - No Connect */
+	GPIO_END
+};
+
+/* SCORE GPIOs (GPIO_S0_SC_XX)*/
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_FUNC1,				/* GPIO_S0_SC[000] - SATA_GP0 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[001] - SATA_GP1 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[002] - SATA_LED_B */
+	GPIO_FUNC1,				/* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */
+	GPIO_FUNC2,				/* GPIO_S0_SC[007] - SD3_WP */
+	GPIO_NC,				/* GPIO_S0_SC[008] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[009] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[010] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[011] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[012] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[013] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[014] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[015] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[016] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[017] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[018] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[019] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[020] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[021] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[022] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[023] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[024] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[025] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[026] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[027] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[028] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[029] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[030] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[031] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[032] - No Connect */
+	GPIO_FUNC1,				/* GPIO_S0_SC[033] - SD3_CLK */
+	GPIO_FUNC1,				/* GPIO_S0_SC[034] - SD3_D0 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[035] - SD3_D1 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[036] - SD3_D2 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[037] - SD3_D3 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[038] - SD3_CD# */
+	GPIO_FUNC1,				/* GPIO_S0_SC[039] - SD3_CMD */
+	GPIO_FUNC1,				/* GPIO_S0_SC[040] - No Connect */
+	GPIO_FUNC1,				/* GPIO_S0_SC[041] - /SD3_PWREN */
+	GPIO_NC,				/* GPIO_S0_SC[042] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[043] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[044] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[045] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[046] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[047] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[048] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[049] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[050] - No Connect */
+	GPIO_FUNC1,				/* GPIO_S0_SC[051] - PCU_SMB_DATA */
+	GPIO_FUNC1,				/* GPIO_S0_SC[052] - PCU_SMB_CLK */
+	GPIO_FUNC1,				/* GPIO_S0_SC[053] - PCU_SMB_ALERT */
+	GPIO_FUNC1,				/* GPIO_S0_SC[054] - ILB_8254_SPKR */
+	GPIO_NC,				/* GPIO_S0_SC[055] - No Connect */
+	GPIO_FUNC0,				/* GPIO_S0_SC[056] - GPIO_S0_SC_56 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[057] - PCU_UART3_TXD */
+	GPIO_NC,				/* GPIO_S0_SC[058] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[059] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[060] - No Connect */
+	GPIO_FUNC1,				/* GPIO_S0_SC[061] - PCU_UART3_RXD */
+	GPIO_FUNC1,				/* GPIO_S0_SC[062] - LPE_I2S_CLK */
+	GPIO_FUNC1,				/* GPIO_S0_SC[063] - LPE_I2S_FRM */
+	GPIO_FUNC1,				/* GPIO_S0_SC[064] - LPE_I2S_DATIN */
+	GPIO_FUNC1,				/* GPIO_S0_SC[065] - LPE_I2S_DATOUT */
+	GPIO_FUNC1,				/* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */
+	GPIO_FUNC1,				/* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */
+	GPIO_FUNC1,				/* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */
+	GPIO_FUNC1,				/* GPIO_S0_SC[070] - SIO_UART1_RXD */
+	GPIO_FUNC1,				/* GPIO_S0_SC[071] - SIO_UART1_TXD */
+	GPIO_NC,				/* GPIO_S0_SC[072] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[073] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[074] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[075] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[076] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[077] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[078] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[079] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[080] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[081] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[082] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[083] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[084] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[085] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[086] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[087] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[088] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[089] - No Connect */
+	GPIO_FUNC1,				/* GPIO_S0_SC[090] - EXP_I2C_SDA */
+	GPIO_FUNC1,				/* GPIO_S0_SC[091] - EXP_I2C_SCL */
+	GPIO_FUNC1,		                /* GPIO_S0_SC[092] - 0R GND? */
+	GPIO_FUNC1,                             /* GPIO_S0_SC[093] - 0R GND? */
+	GPIO_FUNC1,				/* GPIO_S0_SC[094] - SOC_PWM0 */
+	GPIO_FUNC1,				/* GPIO_S0_SC[095] - SOC_PWM1 */
+	GPIO_NC,				/* GPIO_S0_SC[096] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[097] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[098] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[099] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[100] - No Connect */
+	GPIO_NC,				/* GPIO_S0_SC[101] - No Connect */
+	GPIO_END
+};
+
+/* SSUS GPIOs (GPIO_S5) */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_NC,				/* GPIO_S5[00] - No Connect */
+	GPIO_FUNC6,				/* GPIO_S5[01] - PMC_WAKE_PCIE[1] */
+	GPIO_FUNC6,				/* GPIO_S5[02] - PMC_WAKE_PCIE[2] */
+	GPIO_FUNC6,				/* GPIO_S5[03] - PMC_WAKE_PCIE[3] */
+	GPIO_NC,				/* GPIO_S5[04] - No Connect */
+	GPIO_NC,				/* GPIO_S5[05] - No Connect */
+	GPIO_NC,				/* GPIO_S5[06] - No Connect */
+	GPIO_NC,				/* GPIO_S5[07] - No Connect */
+	GPIO_NC,				/* GPIO_S5[08] - No Connect */
+	GPIO_NC,				/* GPIO_S5[09] - No Connect */
+	GPIO_OUT_HIGH,				/* GPIO_S5[10] - GPIO_S5_10_UNLOCK */
+	GPIO_FUNC0,				/* GPIO_S5[11] - SUSPWRDNACK */
+	GPIO_NC,				/* GPIO_S5[12] - No Connect */
+	GPIO_NC,				/* GPIO_S5[13] - No Connect */
+	GPIO_FUNC1,				/* GPIO_S5[14] - GPIO_S514_J20 */
+	GPIO_FUNC0,				/* GPIO_S5[15] - PMC_WAKE_PCIE[0] */
+	GPIO_FUNC(1, PULL_UP, 2K),		/* GPIO_S5[16] - No Connect */
+	GPIO_NC,				/* GPIO_S5[17] - No Connect */
+	GPIO_FUNC1,				/* GPIO_S5[18] - T360 */
+	GPIO_FUNC0,				/* GPIO_S5[19] - SOC_USB_HOST_OC0 */
+	GPIO_FUNC0,				/* GPIO_S5[20] - SOC_USB_HOST_OC1 */
+	GPIO_FUNC0,				/* GPIO_S5[21] - SOC_SPI_CS1B */
+	GPIO_NC,				/* GPIO_S5[22] - No Connect */
+	GPIO_NC,				/* GPIO_S5[23] - No Connect */
+	GPIO_NC,				/* GPIO_S5[24] - No Connect */
+	GPIO_NC,				/* GPIO_S5[25] - No Connect */
+	GPIO_NC,				/* GPIO_S5[26] - No Connect */
+	GPIO_FUNC(0, PULL_DISABLE, 10K),	/* GPIO_S5[27] - SW450-1 */
+	GPIO_FUNC(0, PULL_DISABLE, 10K),	/* GPIO_S5[28] - SW450-2 */
+	GPIO_FUNC(0, PULL_DISABLE, 10K),	/* GPIO_S5[29] - SW450-3 */
+	GPIO_FUNC(0, PULL_DISABLE, 10K),        /* GPIO_S5[30] - SW450-4 */
+	GPIO_NC,				/* GPIO_S5[31] - No Connect */
+	GPIO_NC,				/* GPIO_S5[32] - No Connect */
+	GPIO_NC,				/* GPIO_S5[33] - No Connect */
+	GPIO_NC,				/* GPIO_S5[34] - No Connect */
+	GPIO_NC,				/* GPIO_S5[35] - No Connect */
+	GPIO_NC,				/* GPIO_S5[36] - No Connect */
+	GPIO_NC,				/* GPIO_S5[37] - No Connect */
+	GPIO_NC,				/* GPIO_S5[38] - No Connect */
+	GPIO_NC,				/* GPIO_S5[39] - No Connect */
+	GPIO_NC,				/* GPIO_S5[40] - No Connect */
+	GPIO_NC,				/* GPIO_S5[41] - No Connect */
+	GPIO_NC,				/* GPIO_S5[42] - No Connect */
+	GPIO_NC,				/* GPIO_S5[43] - No Connect */
+	GPIO_END
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus = gpssus_gpio_map,
+	.core_dirq = NULL,
+	.sus_dirq = NULL,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/esd/atom15/irqroute.c b/src/mainboard/esd/atom15/irqroute.c
new file mode 100644
index 0000000000..db8c512a43
--- /dev/null
+++ b/src/mainboard/esd/atom15/irqroute.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/esd/atom15/irqroute.h b/src/mainboard/esd/atom15/irqroute.h
new file mode 100644
index 0000000000..f8660693e5
--- /dev/null
+++ b/src/mainboard/esd/atom15/irqroute.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef IRQROUTE_H
+#define IRQROUTE_H
+
+#include <soc/intel/fsp_baytrail/baytrail/irq.h>
+#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h>
+
+/*
+ *IR02h GFX      INT(A) 	- PIRQ A
+ *IR10h EMMC	 INT(ABCD)	- PIRQ DEFG
+ *IR11h SDIO     INT(A) 	- PIRQ B
+ *IR12h SD       INT(A) 	- PIRQ C
+ *IR13h SATA     INT(A) 	- PIRQ D
+ *IR14h XHCI     INT(A) 	- PIRQ E
+ *IR15h LP Audio INT(A) 	- PIRQ F
+ *IR17h MMC      INT(A) 	- PIRQ F
+ *IR18h SIO      INT(ABCD)	- PIRQ BADC
+ *IR1Ah TXE      INT(A)		- PIRQ F
+ *IR1Bh HD Audio INT(A)		- PIRQ G
+ *IR1Ch PCIe     INT(ABCD)	- PIRQ EFGH
+ *IR1Dh EHCI     INT(A)		- PIRQ D
+ *IR1Eh SIO      INT(ABCD)	- PIRQ BDEF
+ *IR1Fh LPC      INT(ABCD)	- PIRQ HGBC
+ */
+
+/* PCIe bridge routing */
+#define BRIDGE1_DEV	PCIE_DEV
+
+/* PCI bridge IRQs need to be updated in both tables and need to match */
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV,    E, F, G, H)
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,     A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,    D, E, F, G), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,    B, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,      C, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,    D, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,    E, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,     F, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,   F, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,    B, A, D, C), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,     F, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,     G, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,    D, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,    B, D, E, F), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,     H, G, B, C)
+
+/*
+ * Route each PIRQ[A-H] to a PIC IRQ[0-15]
+ * Reserved: 0, 1, 2, 8, 13
+ * PS2 keyboard: 12
+ * ACPI/SCI: 9
+ * Floppy: 6
+ */
+#define PIRQ_PIC_ROUTES \
+	PIRQ_PIC(A,  3), \
+	PIRQ_PIC(B,  5), \
+	PIRQ_PIC(C,  7), \
+	PIRQ_PIC(D, 10), \
+	PIRQ_PIC(E, 11), \
+	PIRQ_PIC(F, 12), \
+	PIRQ_PIC(G, 14), \
+	PIRQ_PIC(H, 15)
+
+#endif /* IRQROUTE_H */
diff --git a/src/mainboard/esd/atom15/mainboard.c b/src/mainboard/esd/atom15/mainboard.c
new file mode 100644
index 0000000000..70f96fc45e
--- /dev/null
+++ b/src/mainboard/esd/atom15/mainboard.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+
+/*
+ * mainboard_enable is executed as first thing after enumerate_buses().
+ * This is the earliest point to add customization.
+ */
+static void mainboard_enable(device_t dev)
+{
+}
+
+/*
+ * mainboard_final is executed as one of the last items before loading the
+ * payload.
+ *
+ * This is the latest point to add customization.
+ */
+static void mainboard_final(void *chip_info)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+	.final = mainboard_final,
+};
diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c
new file mode 100644
index 0000000000..89fc9de8bb
--- /dev/null
+++ b/src/mainboard/esd/atom15/romstage.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baytrail/romstage.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <baytrail/gpio.h>
+#include "chip.h"
+
+/**
+ * /brief mainboard call for setup that needs to be done before fsp init
+ *
+ */
+void early_mainboard_romstage_entry()
+{
+
+}
+
+/**
+ * Get function disables - most of these will be done automatically
+ * @param fd_mask
+ * @param fd2_mask
+ */
+void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
+{
+
+}
+
+/**
+ * /brief mainboard call for setup that needs to be done after fsp init
+ *
+ */
+void late_mainboard_romstage_entry()
+{
+
+	configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
+	configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
+	configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
+	configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
+
+	printk(0, "SW450: %d %d %d %d\n",
+			read_ssus_gpio(27),
+			read_ssus_gpio(28),
+			read_ssus_gpio(29),
+			read_ssus_gpio(30) );
+
+}
+
+void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
+{
+	UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
+	u8 use_xhci = UpdData->PcdEnableXhci;
+
+	/* Update XHCI UPD value if required */
+	get_option(&use_xhci, "use_xhci_over_ehci");
+	if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
+		UpdData->PcdEnableXhci = use_xhci;
+		printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
+			UpdData->PcdEnableXhci?"Enabled":"Disabled");
+	}
+
+	return;
+}