mb/facebook/fbg1701: separate cpld support

Move all code involving the cpld to a single file.
Rename mainboard_read_pcb_version() to cpld_read_pcb_version().

BUG=N/A
TEST=tested on fbg1701 board

Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 72 insertions, 25 deletions

diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc
index c41447004a..734129187b 100644
--- a/src/mainboard/facebook/fbg1701/Makefile.inc
+++ b/src/mainboard/facebook/fbg1701/Makefile.inc
@@ -24,6 +24,7 @@ endif
 
 bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c
 
+ramstage-y += cpld.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
 ramstage-y += irqroute.c
@@ -31,6 +32,8 @@ ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c
 ramstage-y += ramstage.c
 ramstage-y += w25q64.c
 
+romstage-y += cpld.c
+
 cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp
 logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME))
 logo.bmp-type := raw
diff --git a/src/mainboard/facebook/fbg1701/cpld.c b/src/mainboard/facebook/fbg1701/cpld.c
new file mode 100644
index 0000000000..7d1117f6ad
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/cpld.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include "cpld.h"
+
+/* CPLD definitions */
+#define CPLD_PCB_VERSION_PORT 0x283
+#define CPLD_PCB_VERSION_MASK 0xF0
+#define CPLD_PCB_VERSION_BIT 4
+
+#define CPLD_RESET_PORT 0x287
+#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20
+#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00
+
+/* Reset DSI bridge */
+void cpld_reset_bridge(void)
+{
+	outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT);
+	outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT);
+}
+
+/* Read PCB version */
+unsigned int cpld_read_pcb_version(void)
+{
+	return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> CPLD_PCB_VERSION_BIT);
+}
diff --git a/src/mainboard/facebook/fbg1701/cpld.h b/src/mainboard/facebook/fbg1701/cpld.h
new file mode 100644
index 0000000000..9604cfbc51
--- /dev/null
+++ b/src/mainboard/facebook/fbg1701/cpld.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CPLD_H
+#define CPLD_H
+
+unsigned int cpld_read_pcb_version(void);
+void cpld_reset_bridge(void);
+
+#endif
diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c
index a8cb34c744..8524b24000 100644
--- a/src/mainboard/facebook/fbg1701/mainboard.c
+++ b/src/mainboard/facebook/fbg1701/mainboard.c
@@ -16,10 +16,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/device.h>
-#include "mainboard.h"
-#include "onboard.h"
 
 /*
  * Declare the resources we are using
@@ -39,13 +36,6 @@ static void mainboard_reserve_resources(struct device *dev)
 	res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-/* Read PCB version */
-unsigned int mainboard_read_pcb_version(void)
-{
-	return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >>
-		CPLD_PCB_VERSION_BIT);
-}
-
 /*
  * mainboard_enable is executed as first thing after
  * enumerate_buses().
diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/mainboard.h
index 3cace548b3..82f1b9939c 100644
--- a/src/mainboard/facebook/fbg1701/mainboard.h
+++ b/src/mainboard/facebook/fbg1701/mainboard.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Eltan B.V.
+ * Copyright (C) 2018-2019 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,7 +16,6 @@
 #ifndef MAINBOARD_H
 #define MAINBOARD_H
 
-unsigned int mainboard_read_pcb_version(void);
 void *load_logo(size_t *logo_size);
 
 #endif
diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h
index 2c78d15961..cb784daf69 100644
--- a/src/mainboard/facebook/fbg1701/onboard.h
+++ b/src/mainboard/facebook/fbg1701/onboard.h
@@ -21,15 +21,6 @@
 /* SD CARD gpio */
 #define SDCARD_CD 81 /* Not used */
 
-
-/* CPLD definitions */
-#define CPLD_PCB_VERSION_PORT 0x283
-#define CPLD_PCB_VERSION_MASK 0xF0
-#define CPLD_PCB_VERSION_BIT  4
-
-#define CPLD_RESET_PORT 0x287
-#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20
-#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00
 #define ITE8528_CMD_PORT 0x6E
 #define ITE8528_DATA_PORT 0x6F
 
diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c
index 980a6ccdb7..e2b4ac3145 100644
--- a/src/mainboard/facebook/fbg1701/ramstage.c
+++ b/src/mainboard/facebook/fbg1701/ramstage.c
@@ -19,7 +19,7 @@
 #include <soc/ramstage.h>
 #include <soc/smbus.h>
 #include "mainboard.h"
-#include "onboard.h"
+#include "cpld.h"
 
 struct edp_data {
 	u8 payload_length;
@@ -326,16 +326,19 @@ static void mainboard_configure_edp_bridge(void)
 {
 	const struct edp_data *edptable;
 	unsigned int loops;
+	unsigned int pcb_version;
 	int status;
 
-	if (mainboard_read_pcb_version() < 7)
+	pcb_version = cpld_read_pcb_version();
+	printk(BIOS_DEBUG, "PCB version: %x\n", pcb_version);
+
+	if (pcb_version < 7)
 		edptable = b101uan01_table;
 	else
 		edptable = b101uan08_table;
 
 	/* reset bridge */
-	outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT);
-	outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT);
+	cpld_reset_bridge();
 
 	while (edptable->payload_length) {
 		loops = 5;