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authorBenjamin Doron <benjamin.doron00@gmail.com>2020-10-12 04:19:42 +0000
committerNico Huber <nico.h@gmx.de>2020-10-16 22:03:34 +0000
commitb53858bacee1b3561ab0c70e3f82196f4e7eb6cb (patch)
tree71a05fe3201906f4ef52a81c0848a64ce994dbd2 /src/mainboard/facebook
parent3f1de9add900305730a28be919a21a682ae6b224 (diff)
downloadcoreboot-b53858bacee1b3561ab0c70e3f82196f4e7eb6cb.tar.xz
soc/intel/skylake: Rename PcieRpAspm devicetree config
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/facebook')
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 95e2565a80..bb11d064b3 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -151,7 +151,7 @@ chip soc/intel/skylake
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[2]" = "1"
# Disable Aspm
- register "PcieRpAspm[2]" = "AspmDisabled"
+ register "pcie_rp_aspm[2]" = "AspmDisabled"
# PCIE Port 4 disabled
# PCIE Port 5 x1 -> MODULE i219
@@ -166,7 +166,7 @@ chip soc/intel/skylake
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[5]" = "1"
# Disable Aspm
- register "PcieRpAspm[5]" = "AspmDisabled"
+ register "pcie_rp_aspm[5]" = "AspmDisabled"
# PCIE Port 7 Disabled
# PCIE Port 8 Disabled
@@ -184,7 +184,7 @@ chip soc/intel/skylake
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[8]" = "1"
# Disable Aspm
- register "PcieRpAspm[8]" = "AspmDisabled"
+ register "pcie_rp_aspm[8]" = "AspmDisabled"
# USB 2.0 Enable all ports
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2