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authorArthur Heymans <arthur@aheymans.xyz>2019-01-15 20:14:33 +0100
committerArthur Heymans <arthur@aheymans.xyz>2019-05-25 15:49:27 +0000
commit99e578e3c1697028957f25efc7c14d1cb4d405dc (patch)
tree44853df46744994d5caf3172a579f9d92252155b /src/mainboard/foxconn/d41s
parentc752c500fbcc055e8cdfb30a2e523e8a9349b79f (diff)
downloadcoreboot-99e578e3c1697028957f25efc7c14d1cb4d405dc.tar.xz
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/foxconn/d41s')
-rw-r--r--src/mainboard/foxconn/d41s/Makefile.inc2
-rw-r--r--src/mainboard/foxconn/d41s/early_init.c (renamed from src/mainboard/foxconn/d41s/romstage.c)3
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc
index f3d7e76263..057b5bfcd3 100644
--- a/src/mainboard/foxconn/d41s/Makefile.inc
+++ b/src/mainboard/foxconn/d41s/Makefile.inc
@@ -1,2 +1,4 @@
+romstage-y += early_init.c
+bootblock-y += early_init.c
ramstage-y += cstates.c
romstage-y += gpio.c
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/early_init.c
index cdd12dc3ac..6568d96139 100644
--- a/src/mainboard/foxconn/d41s/romstage.c
+++ b/src/mainboard/foxconn/d41s/early_init.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/pineview/pineview.h>
@@ -23,7 +24,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)
-void mb_enable_lpc(void)
+void bootblock_mainboard_early_init(void)
{
/* Disable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);