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author | Duncan Laurie <dlaurie@google.com> | 2019-01-08 15:13:15 -0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-10 12:15:16 +0000 |
commit | 13f58e47ed995a73b2ae57c25b98afed84675783 (patch) | |
tree | 482277a6cf94295ea4c7f68d4064060796363e57 /src/mainboard/foxconn/g41s-k/acpi | |
parent | 61b22cb930388510d057cdd79392529660fa4a8c (diff) | |
download | coreboot-13f58e47ed995a73b2ae57c25b98afed84675783.tar.xz |
mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP
1) Add a Platform Data Region called SI_PDR which is allocated in the flash
descriptor for this platform
2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile
storage.
3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG
so it is clear they are associated.
4) Move the RW_DIAG region to the start of the RW region so that once we can
re-enable a larger BIOS region this sub-region will be in the uncached area
since it is not accessed on a normal boot.
BUG=b:119435206
TEST=tested on Arcada board to ensure expected regions are present
Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k/acpi')
0 files changed, 0 insertions, 0 deletions