diff options
author | Samuel Holland <samuel@sholland.org> | 2017-06-03 03:53:33 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-06-12 04:41:02 +0200 |
commit | 82651463e38aef32c5fc4012c5b9f3ac5b4e2104 (patch) | |
tree | 75b7cb4ee8872c87fc1f9b73a679031939917592 /src/mainboard/foxconn/g41s-k/acpi | |
parent | ab7127771d59825234717b9a1e6e0e3f84fa4277 (diff) | |
download | coreboot-82651463e38aef32c5fc4012c5b9f3ac5b4e2104.tar.xz |
mb/foxconn/g41s-k: add new mainboard
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O.
Tested, working:
* Booting Linux 4.11.3 and Windows 8.1 from USB and HDD
* Resume from S3 (Linux and Windows)
* Native raminit (DDR2-800)
* Native graphics init (SeaBIOS, Linux)
* Graphics init with VGA BIOS (SeaBIOS, Windows)
* PCI-E x16 PEG slot, PCI-E x1 slot from southbridge
* Realtek ALC888 HD Audio (including front panel and jack detection)
* Realtek R8168 Gigabit LAN
* Both SATA ports
* USB 1.1 and 2.0 devices (keyboard, mass storage)
* PC speaker beep
* COM header
* Super I/O Environment controller (temps, voltage, fans)
* PS/2 keyboard and mouse
* Flashing with `flashrom -p internal`
* 1MiB and 2MiB SPI flash chips
* CMOS gfx_uma_size
Appears, OS driver loads, but otherwise untested:
* IrDA header
* CIR header
* TPM header
Untested:
* S/PDIF digital audio
Tested, known broken:
* CMOS power_on_after_fail
* USB keyboard in secondary payloads
Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20027
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k/acpi')
-rw-r--r-- | src/mainboard/foxconn/g41s-k/acpi/ec.asl | 1 | ||||
-rw-r--r-- | src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl | 46 | ||||
-rw-r--r-- | src/mainboard/foxconn/g41s-k/acpi/platform.asl | 28 | ||||
-rw-r--r-- | src/mainboard/foxconn/g41s-k/acpi/superio.asl | 35 | ||||
-rw-r--r-- | src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl | 79 |
5 files changed, 189 insertions, 0 deletions
diff --git a/src/mainboard/foxconn/g41s-k/acpi/ec.asl b/src/mainboard/foxconn/g41s-k/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..9d10d81d69 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> + * Copyright (C) 2017 Samuel Holland <samuel@sholland.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + + Package() { 0x0001ffff, 0, 0, 0x11}, + Package() { 0x0001ffff, 1, 0, 0x12}, + Package() { 0x0001ffff, 2, 0, 0x13}, + Package() { 0x0001ffff, 3, 0, 0x10}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/foxconn/g41s-k/acpi/platform.asl b/src/mainboard/foxconn/g41s-k/acpi/platform.asl new file mode 100644 index 0000000000..bda0df74b1 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl new file mode 100644 index 0000000000..3811c2f1ad --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2017 Samuel Holland <samuel@sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8720F_SHOW_SP1 +#undef IT8720F_SHOW_SP2 +#undef IT8720F_SHOW_EC +#undef IT8720F_SHOW_KBCK +#undef IT8720F_SHOW_KBCM +#undef IT8720F_SHOW_GPIO +#undef IT8720F_SHOW_CIR +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8720F_SHOW_SP1 1 +#define IT8720F_SHOW_SP2 1 +#define IT8720F_SHOW_EC 1 +#define IT8720F_SHOW_KBCK 1 +#define IT8720F_SHOW_KBCM 1 +#define IT8720F_SHOW_GPIO 1 +#define IT8720F_SHOW_CIR 1 +#include <superio/ite/it8720f/acpi/superio.asl> diff --git a/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000000..8c8afcb9b5 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> + * Copyright (C) 2017 Samuel Holland <samuel@sholland.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* PEG 0:01.0 */ + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0001ffff, 1, 0, 0x11 }, + Package() { 0x0001ffff, 2, 0, 0x12 }, + Package() { 0x0001ffff, 3, 0, 0x13 }, + /* Internal GFX 0:02.0 */ + Package() { 0x0002ffff, 0, 0, 0x10 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 0x10 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 0x10 }, + Package() { 0x001cffff, 1, 0, 0x11 }, + Package() { 0x001cffff, 2, 0, 0x12 }, + Package() { 0x001cffff, 3, 0, 0x13 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 0x17 }, + Package() { 0x001dffff, 1, 0, 0x13 }, + Package() { 0x001dffff, 2, 0, 0x12 }, + Package() { 0x001dffff, 3, 0, 0x10 }, + /* PCI Bridge 0x1e.0 */ + Package() { 0x001effff, 0, 0, 0x11 }, + Package() { 0x001effff, 1, 0, 0x14 }, + /* PATA/SATA/SMBUS 0:1f.x */ + Package() { 0x001fffff, 0, 0, 0x12 }, + Package() { 0x001fffff, 1, 0, 0x13 }, + }) + } Else { + Return (Package() { + /* PEG 0:01.0 */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* Internal GFX 0:02.0 */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCI Bridge 0x1e.0 */ + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + /* PATA/SATA/SMBUS 0:1f.x */ + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} |