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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-15 22:02:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-11-12 14:06:37 +0000 |
| commit | b9d2589ca40026b543ecb5b008ce0d1bc346bf53 (patch) | |
| tree | 87cac45cfc1c1211f012aaa76b8a87162f092aff /src/mainboard/foxconn/g41s-k/devicetree.cb | |
| parent | 81dd52b7eb663c6098de5d8c7c56ed572c91b539 (diff) | |
| download | coreboot-b9d2589ca40026b543ecb5b008ce0d1bc346bf53.tar.xz | |
mb/*/*: Harmonise FD and devicetree on boards featuring ICH7
On some boards the devicetree and Function Disable register did not
match. In this case the FD values are put in the devicetree as these
were the values that were actually used in practice.
A complete devicetree will make it easier to automatically disable
devices in ramstage.
Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k/devicetree.cb')
| -rw-r--r-- | src/mainboard/foxconn/g41s-k/devicetree.cb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index e57436ae7c..a63845760c 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -66,6 +66,8 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x105b 0x0dda end @@ -82,6 +84,8 @@ chip northbridge/intel/x4x # Northbridge subsystemid 0x105b 0x0dda end device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x105b 0x0dda chip superio/ite/it8720f # Super I/O @@ -181,9 +185,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1f.3 on # SMbus subsystemid 0x105b 0x0dda end - device pci 1f.4 off end - device pci 1f.5 off end - device pci 1f.6 off end end end end |