diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-15 21:38:39 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-10 12:17:10 +0000 |
commit | f3e50fc68186fbfa93f77d05f182bf0435e745ab (patch) | |
tree | 12fd4e95d9ceab386dda329cb31f1f79786a77d0 /src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl | |
parent | 13f58e47ed995a73b2ae57c25b98afed84675783 (diff) | |
download | coreboot-f3e50fc68186fbfa93f77d05f182bf0435e745ab.tar.xz |
mb/foxconn/g41s-k: Add g41m variant
Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit with VGA, DVI (HDMI slot unpopulated)
- PS2 Keyboard
- SATA
- PEG
- S3 resume
What does not work:
- Using the second DIMM slot on a channel
G41 can only handle 2 ranks per channel and on this mainboard 1 rank
per DIMM slot. Supporting this would require too much raminit rework
and is not worth it (at least for me)
Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl')
-rw-r--r-- | src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..f1f3462d49 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> + * Copyright (C) 2017 Samuel Holland <samuel@sholland.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. +m * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x12}, + Package() { 0x0001ffff, 1, 0, 0x13}, + Package() { 0x0001ffff, 2, 0, 0x10}, + Package() { 0x0001ffff, 3, 0, 0x11}, + + Package() { 0x0002ffff, 0, 0, 0x11}, + Package() { 0x0002ffff, 1, 0, 0x12}, + Package() { 0x0002ffff, 2, 0, 0x13}, + Package() { 0x0002ffff, 3, 0, 0x10}, + }) +} Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0}, + }) +} |