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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-16 14:02:25 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-18 19:03:22 +0000
commit157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 (patch)
tree4562bd212e40d0832fa893935d85a06d82f8a897 /src/mainboard/foxconn/g41s-k
parent146c09823333c52e8bbca98465ccc8512ec1daa2 (diff)
downloadcoreboot-157b189f6b97b6e9ecd8d29edbbd045fbbc231f5.tar.xz
cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k')
-rw-r--r--src/mainboard/foxconn/g41s-k/romstage.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index ec4541f92e..16c3b47a30 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -17,7 +17,6 @@
*/
#include <console/console.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <device/pci_ops.h>
#include <northbridge/intel/x4x/iomap.h>
@@ -81,7 +80,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
}
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
// ch0 ch1
#if CONFIG(BOARD_FOXCONN_G41S_K)
@@ -101,7 +100,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init();
- report_bist_failure(bist);
enable_smbus();
x4x_early_init();