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| author | Vagiz Trakhanov <rakkin@autistici.org> | 2017-09-28 14:21:54 +0000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-22 02:19:15 +0000 |
| commit | 17c577153042b6559bf7a9dca6ae9f644b18d770 (patch) | |
| tree | ee9c3c2381a73e6b9c7d36521a1af1c99aa2c6ac /src/mainboard/foxconn | |
| parent | c85890d0d8887462e72837c3ae6dd5b6842a81cb (diff) | |
| download | coreboot-17c577153042b6559bf7a9dca6ae9f644b18d770.tar.xz | |
superio/ite/common: Add temperature offset
Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.
As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.
I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.
TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/foxconn')
| -rw-r--r-- | src/mainboard/foxconn/g41s-k/devicetree.cb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index fae89e65fb..e57436ae7c 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -85,9 +85,10 @@ chip northbridge/intel/x4x # Northbridge device pci 1f.0 on # ISA bridge subsystemid 0x105b 0x0dda chip superio/ite/it8720f # Super I/O - register "TMPIN1" = "THERMAL_DIODE" - register "TMPIN2" = "THERMAL_RESISTOR" - register "TMPIN3" = "THERMAL_MODE_DISABLED" + register "TMPIN1.mode" = "THERMAL_DIODE" + register "TMPIN1.offset" = "0" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" register "ec.vin_mask" = "VIN_ALL" |