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authorArthur Heymans <arthur@aheymans.xyz>2018-12-15 23:46:48 +0100
committerNico Huber <nico.h@gmx.de>2019-01-08 14:29:13 +0000
commit6267f5dd11aa43fd0bd84f84192db4ddaffa8575 (patch)
tree75ee8cc7fce69523e4fde510ec3330823807a40a /src/mainboard/foxconn
parent79a7ad6dda8a5a4272b6a59cef750af2f2585dc2 (diff)
downloadcoreboot-6267f5dd11aa43fd0bd84f84192db4ddaffa8575.tar.xz
sb/intel/i82801gx: Autodisable functions based on devicetree
This removes the need to synchronize the devicetree and the romstage writing to FD. Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30244 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/foxconn')
-rw-r--r--src/mainboard/foxconn/d41s/romstage.c4
-rw-r--r--src/mainboard/foxconn/g41s-k/romstage.c3
2 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c
index 2d64bef8c0..194bd7373e 100644
--- a/src/mainboard/foxconn/d41s/romstage.c
+++ b/src/mainboard/foxconn/d41s/romstage.c
@@ -75,10 +75,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
-
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | FD_PATA;
- RCBA32(FD) |= 1;
}
void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 5ea41ea194..a695c53505 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -66,8 +66,7 @@ static void mb_lpc_setup(void)
RCBA8(OIC) = 0x03;
RCBA8(OIC);
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN |
- FD_ACMOD | FD_ACAUD | FD_PATA | 1;
+ RCBA32(FD) |= FD_INTLAN;
RCBA32(CG) = 0x00000001;
}