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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-27 00:12:35 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-05 09:27:53 +0000 |
| commit | d6f3dd83dc7d8bb66e29c489e82d4736779d7b6f (patch) | |
| tree | 2761d3a4fc723e796b96ce1034f86defc51cd21d /src/mainboard/foxconn | |
| parent | 931ed7faa97b3f2954123ba8d0b5fd330ef10bf3 (diff) | |
| download | coreboot-d6f3dd83dc7d8bb66e29c489e82d4736779d7b6f.tar.xz | |
nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout
Especially on ICH7 failing to do so results in i2c block read being
unusable. On ICH10 this problem doesn't manifest itself that much.
This moves disabling the watchdog reboot to the northbridge code like
i945 (even though it technically is southbridge stuff).
TESTED on Intel DG41WV: hacking on raminit is much nicer since no
need to do a hard power down for +4s are needed to clear the timeouts.
Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/foxconn')
| -rw-r--r-- | src/mainboard/foxconn/g41s-k/romstage.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 2a704a3c66..ba07e45e99 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -91,9 +91,6 @@ void mainboard_romstage_entry(unsigned long bist) timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); - /* Disable watchdog timer. */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Set up southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); |