diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-25 15:18:25 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-04 23:02:27 +0100 |
| commit | ab83ef02c7131d23a28c6acbd79e6cd9997dcec8 (patch) | |
| tree | 2a04f314104c3a43e6eaaacd5cceb5ec8db81386 /src/mainboard/getac/p470/devicetree.cb | |
| parent | 9c4f1b8e05fbd659ebdb3d03d811f1ad39079a1a (diff) | |
| download | coreboot-ab83ef02c7131d23a28c6acbd79e6cd9997dcec8.tar.xz | |
i82801gx: Handle whole FADT in southbridge.
Do all the handling in SB code with few parameters from devicetree.cb
instead of having mobo callbacks.
Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7199
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/getac/p470/devicetree.cb')
| -rw-r--r-- | src/mainboard/getac/p470/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 6256ca10ab..d1b06a0c98 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -60,6 +60,10 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" + register "c3_latency" = "85" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe port 1 device pci 1c.1 on end # PCIe port 2 |