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authorArthur Heymans <arthur@aheymans.xyz>2016-11-29 14:13:43 +0100
committerMartin Roth <martinroth@google.com>2017-01-06 18:14:00 +0100
commit62902ca45de871aa59657dd8ec1858c301595634 (patch)
tree43b21ab2ec87ec5b41f875efb69be8bb494b0fa7 /src/mainboard/getac/p470
parent40843efe5d6dddff19a0d7c8c5fe84c75448e739 (diff)
downloadcoreboot-62902ca45de871aa59657dd8ec1858c301595634.tar.xz
sb/ich7: Use common/gpio.h to set up GPIOs
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/getac/p470')
-rw-r--r--src/mainboard/getac/p470/Makefile.inc1
-rw-r--r--src/mainboard/getac/p470/gpio.c115
-rw-r--r--src/mainboard/getac/p470/romstage.c28
3 files changed, 119 insertions, 25 deletions
diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc
index 07d9918bd0..ed9d39cec6 100644
--- a/src/mainboard/getac/p470/Makefile.inc
+++ b/src/mainboard/getac/p470/Makefile.inc
@@ -14,3 +14,4 @@
##
ramstage-y += cstates.c
+romstage-y += gpio.c
diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c
new file mode 100644
index 0000000000..be52a86ce1
--- /dev/null
+++ b/src/mainboard/getac/p470/gpio.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_OUTPUT,
+ .gpio14 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio13 = GPIO_LEVEL_HIGH,
+ .gpio14 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 20130f27d2..d1552a6599 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -34,34 +34,10 @@
#include <timestamp.h>
#include "option_table.h"
-void setup_ich7_gpios(void)
+static void setup_special_ich7_gpios(void)
{
u32 gpios;
- printk(BIOS_DEBUG, " GPIOS...");
- /* General Registers */
- outl(0x1f28f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
- outl(0xe0e809c3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
- // Power On value is eede1fbf, we set: (TODO explain why)
- // -- [21] = 1
- // -- [20] = 0
- // -- [18] = 0
- // -- [17] = 0
- // -- [13] = 1
- // -- [05] = 0
- // -- [04] = 0
- // -- [03] = 0
- // -- [02] = 0
- // We should probably do this explicitly bitwise, see below.
- outl(0xeee83f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
- /* Output Control Registers */
- outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
- /* Input Control Registers */
- outl(0x00000180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
- outl(0x000000e6, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
- outl(0x000000d0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
- outl(0x00000034, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
-
printk(BIOS_SPEW, "\n Initializing drive bay...\n");
gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
gpios |= (1 << 0); // GPIO33 = ODD
@@ -297,6 +273,8 @@ void mainboard_romstage_entry(unsigned long bist)
*/
i945_early_initialization();
+ setup_special_ich7_gpios();
+
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */