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authorArthur Heymans <arthur@aheymans.xyz>2017-08-15 20:59:09 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-01-14 21:43:25 +0000
commitb451df2f400ba12fff440247330f8b57a93034bd (patch)
tree8bb52821a42aaaea2e614910d97b1ae4e690b7c2 /src/mainboard/getac/p470
parente4a016ff17b455a8acd0ea72b30caabb622ce224 (diff)
downloadcoreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.xz
mb/*/*/romstage.c: Clean up targets with i82801gx
Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/getac/p470')
-rw-r--r--src/mainboard/getac/p470/romstage.c42
1 files changed, 22 insertions, 20 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index d1552a6599..e58ef1bda6 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -57,21 +57,23 @@ static void setup_special_ich7_gpios(void)
static void ich7_enable_lpc(void)
{
int lpt_en = 0;
- if (read_option(lpt, 0) != 0) {
- lpt_en = 1 << 2; // enable LPT
- }
+ if (read_option(lpt, 0) != 0)
+ lpt_en = LPT_LPC_EN;
+
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+ | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
+ | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN);
// Enable 0x02e0 - 0x2ff
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);
// Enable 0x600 - 0x6ff
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);
// Enable 0x68 - 0x6f
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
@@ -150,23 +152,23 @@ static void rcba_config(void)
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042220;
+ RCBA32(D31IP) = 0x00042220;
/* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
+ RCBA32(D28IP) = 0x00214321;
/* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
+ RCBA16(D31IR) = 0x0232;
+ RCBA16(D30IR) = 0x3246;
+ RCBA16(D29IR) = 0x0237;
+ RCBA16(D28IR) = 0x3201;
+ RCBA16(D27IR) = 0x3216;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
- RCBA32(0x3418) |= (1 << 0); // Required.
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
+ RCBA32(FD) |= (1 << 0); // Required.
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
@@ -221,7 +223,7 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);