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authorPatrick Georgi <patrick.georgi@secunet.com>2011-01-27 07:39:38 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2011-01-27 07:39:38 +0000
commita470019b7a19e164b5dc93b1d541dc4158edbeda (patch)
tree48156b3fb7f795cbe3241f787b642460aa03a29d /src/mainboard/getac
parenta5c949eff288af3eb4caffec57a3724c497150de (diff)
downloadcoreboot-a470019b7a19e164b5dc93b1d541dc4158edbeda.tar.xz
Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the variable reset, it's not. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/getac')
-rw-r--r--src/mainboard/getac/p470/cmos.layout3
-rw-r--r--src/mainboard/getac/p470/devicetree.cb4
-rw-r--r--src/mainboard/getac/p470/romstage.c7
3 files changed, 11 insertions, 3 deletions
diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout
index f86e479df5..130f1cefc6 100644
--- a/src/mainboard/getac/p470/cmos.layout
+++ b/src/mainboard/getac/p470/cmos.layout
@@ -93,7 +93,8 @@ entries
416 512 s 0 boot_devices
928 8 h 0 boot_default
936 1 e 8 cmos_defaults_loaded
-#937 47 r 0 unused
+937 1 e 1 lpt
+#938 46 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index 26939772ad..2929cbee5b 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -86,7 +86,9 @@ chip northbridge/intel/i945
device pnp 2e.1 off # ACPI PM
end
# 2e.2 does not exist
- device pnp 2e.3 off # Parallel port
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 5
end
device pnp 2e.4 on # COM1
io 0x60 = 0x3f8
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index ac71a6b256..270a7bd578 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -34,6 +34,7 @@
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#include "option_table.h"
void setup_ich7_gpios(void)
{
@@ -81,12 +82,16 @@ void setup_ich7_gpios(void)
static void ich7_enable_lpc(void)
{
+ int lpt_en = 0;
+ if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) {
+ lpt_en = 1<<2; // enable LPT
+ }
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
// Enable 0x02e0 - 0x2ff
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
// Enable 0x600 - 0x6ff