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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/mainboard/getac | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
| download | coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/getac')
| -rw-r--r-- | src/mainboard/getac/p470/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/getac/p470/romstage.c | 18 |
2 files changed, 9 insertions, 13 deletions
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 81ee9b17aa..e2001d91d1 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -62,6 +62,10 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x001c02e1" + register "gen2_dec" = "0x00fc0601" + register "gen3_dec" = "0x00040069" + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe port 1 device pci 1c.1 on end # PCIe port 2 diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 6b5de90e74..e27194aab9 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -51,26 +51,17 @@ static void setup_special_ich7_gpios(void) outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ } -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) lpt_en = LPT_LPC_EN; - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN); - // Enable 0x02e0 - 0x2ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1); - // Enable 0x600 - 0x6ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); - // Enable 0x68 - 0x6f - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -206,7 +197,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); early_superio_config(); /* Set up the console */ |