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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
| commit | 57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch) | |
| tree | 3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/mainboard/getac | |
| parent | 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff) | |
| download | coreboot-57b2ff886e0ce2c92820f5722c8031def3ac94cf.tar.xz | |
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/getac')
| -rw-r--r-- | src/mainboard/getac/p470/romstage.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 5416d0cdae..788f42cb35 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -28,12 +28,9 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <usbdebug.h> - #include <pc80/mc146818rtc.h> - #include <console/console.h> #include <cpu/x86/bist.h> - #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -100,7 +97,6 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); } - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -398,4 +394,3 @@ void main(unsigned long bist) } #endif } - |