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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-07 16:24:28 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-07 16:24:28 +0000
commit6798b478027cb3fd44d52706ad69dee29bae19ba (patch)
treea6cb5f73d04d009d7187a1bd0cf65878857166a0 /src/mainboard/gigabyte/ga-6bxe
parent6f2d20ec490a276a087acad0b3866c0f3ee844c4 (diff)
downloadcoreboot-6798b478027cb3fd44d52706ad69dee29bae19ba.tar.xz
Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.
Also: Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device on various PCI bus:device.function locations. Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. Thus, instead of hardcoding PCI bus:device.function numbers such as PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which works the same on all boards. As an additional benefit this patch also gets rid of one .c file include in romstage.c. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte/ga-6bxe')
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/romstage.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index aafd39453c..e60ca46fa8 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -55,9 +54,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
- /* Enable access to the full ROM chip, needed very early by CBFS. */
- i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
enable_smbus();
dump_spd_registers();
sdram_set_registers();