diff options
| author | Alex James <theracermaster@gmail.com> | 2019-05-15 20:15:47 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-16 20:19:24 +0000 |
| commit | 25b35d317eef9ef5d73bbecc502fdac13a478bf6 (patch) | |
| tree | 0f5f66b0e27ed3d396002841d5751d8e9b0395e8 /src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | |
| parent | d9391837198d838d55ecf853ca70a675f9ca36aa (diff) | |
| download | coreboot-25b35d317eef9ef5d73bbecc502fdac13a478bf6.tar.xz | |
mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups
- Enable LPC TPM support in Kconfig and add pc80/tpm to devicetree
- Enable VBT support in Kconfig and add VBT files extracted from
vendor firmware
- Remove IGPU VBIOS entries from Kconfig
- Remove unused PS2 definitions in superio.asl
- Add PWRB ACPI device entry to mainboard.asl
- Remove duplicate chipset register initialization from mainboard.c
- Move ITE Super I/O configuration to mainboard_config_superio in
romstage.c
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-b75m-d3h/romstage.c')
| -rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index aa5f4840a3..49647850cd 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -25,12 +25,6 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} - void pch_enable_lpc(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | @@ -40,7 +34,10 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} +void mainboard_config_superio(void) +{ /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -87,18 +84,20 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 5, 6 }, }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +void mainboard_early_init(int s3resume) { - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[1], 0x51, id_only); - read_spd (&spd[2], 0x52, id_only); - read_spd (&spd[3], 0x53, id_only); } -void mainboard_early_init(int s3resume) +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); } -void mainboard_config_superio(void) +void mainboard_rcba_config(void) { + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; } |