diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 19:11:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:48:35 +0000 |
| commit | fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch) | |
| tree | af8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/gigabyte/ga-b75m-d3h | |
| parent | 59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff) | |
| download | coreboot-fa5d0f835b1f3bb8907e616913cbf7b91d09ef26.tar.xz | |
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte/ga-b75m-d3h')
| -rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/early_init.c (renamed from src/mainboard/gigabyte/ga-b75m-d3h/romstage.c) | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index f5b33bd644..0abe48248e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -21,3 +21,5 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index a5d4c35b34..0a863fffd2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -30,7 +31,7 @@ void mainboard_pch_lpc_setup(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |