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authorArthur Heymans <arthur@aheymans.xyz>2016-10-24 01:43:17 +0200
committerMartin Roth <martinroth@google.com>2016-11-21 23:58:15 +0100
commit5d0a93d5e74b5d6305f0b96cf04cc818061879d1 (patch)
tree7b098024f87a9a42c86f4fe0609c039d232b997f /src/mainboard/gigabyte/ga-g41m-es2l/acpi
parent53bd26f531d9ee920948a931a03aae23de21f0ce (diff)
downloadcoreboot-5d0a93d5e74b5d6305f0b96cf04cc818061879d1.tar.xz
mb/ga-g41m-es2l: Correctly configure PCI IRQ in ACPI
Obtained from vendor bios DSDT, under "Device (HUB0), Name (_ADR, 0x001E0000)". The schematics also indicate that the INTA-D are hardwired to these PIRQ lines. Change-Id: I8e1c6cb986a2b345a5e1fddd454c7fb12fb8256a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17099 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/acpi')
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl26
1 files changed, 18 insertions, 8 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl
index 0a69f3d3dc..099a53f968 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl
@@ -19,16 +19,26 @@
If (PICM) {
Return (Package() {
- Package() { 0x001effff, 0, 0, 17},
- Package() { 0x001effff, 1, 0, 20},
- Package() { 0x001effff, 2, 0, 16},
- Package() { 0x001effff, 3, 0, 16},
+ Package() { 0x0000ffff, 0, 0, 20},
+ Package() { 0x0000ffff, 1, 0, 19},
+ Package() { 0x0000ffff, 2, 0, 18},
+ Package() { 0x0000ffff, 3, 0, 16},
+
+ Package() { 0x0001ffff, 0, 0, 19},
+ Package() { 0x0001ffff, 1, 0, 18},
+ Package() { 0x0001ffff, 2, 0, 16},
+ Package() { 0x0001ffff, 3, 0, 20},
})
} Else {
Return (Package() {
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0},
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0},
- Package() { 0x001effff, 2, \_SB.PCI0.LPCB.LNKA, 0},
- Package() { 0x001effff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
})
}